Methods and apparatus for power management of a memory cell
Various embodiments of the present technology may comprise a method and apparatus for power management of a memory cell. The memory cell may be configured to operate at various voltage levels to mitigate power dissipation. The memory cell may receive a first voltage level during an active state and receive a second voltage level during an idle state. The active and idle states may be known based on predetermined system parameters. The second voltage level may be selected according to the particular characteristics of the memory cell in order to retain input data.
1. A circuit configured to receive a first voltage, a second voltage, and a control signal, comprising:
a selector circuit responsive to the control signal and configured to selectively supply the first voltage and the second voltage to a memory cell according to the control signal;
wherein the memory cell is configured to:
operate in a first state for a pre-defined first time period that is based on a pre-defined sampling frequency; and
operate in a second state for a pre-defined second time period that is based on the pre-defined sampling frequency; and
wherein the selector circuit is configured to:
supply the first voltage to the memory cell when the memory cell is in the first state; and
supply the second voltage to the memory cell when the memory cell is in the second state.
2. The circuit according to claim 1 , wherein the memory cell is further configured to receive a clock signal having a clock frequency, wherein the clock frequency is the sampling frequency multiplied by a whole number.
3. The circuit according to claim 2 , wherein the first time period is equal to an inverse of the clock frequency.
4. The circuit according to claim 1 , wherein:
when the memory cell operates in the first state, the memory cell is capable of reading and writing data; and
when the memory cell operates in the second state, the memory cell is:
capable of retaining previously-written data; and
incapable of reading and writing new data.
5. The circuit according to claim 1 , wherein the sampling frequency is selected according to a range of human hearing.
6. The circuit according to claim 1 , wherein:
the first voltage is less than a maximum operating voltage of the memory cell and greater than a minimum operating voltage of the memory cell; and
the second voltage is less than the minimum operating voltage of the memory cell and greater than a minimum retention voltage of the memory cell.
7. A method for operating a data processing circuit having at least one memory cell, comprising:
receiving a first voltage and a second voltage;
operating the memory cell in a first state for a pre-defined first time period that is based on a pre-defined sampling frequency;
operating the memory cell in a second state for a pre-defined second time period that is based on the pre-defined sampling frequency;
supplying the first voltage to the memory cell when the memory cell is in the first state; and
supplying the second voltage to the memory cell when the memory cell is in the second state.
8. The method for operating a data processing circuit according to claim 7 , wherein:
the first voltage is less than a maximum operating voltage of the memory cell and greater than a minimum operating voltage of the memory cell; and
the second voltage is less than the minimum operating voltage of the memory cell and greater than a minimum retention voltage of the memory cell.
9. The method for operating a data processing circuit according to claim 7 , wherein:
when the memory cell operates in the first state, the memory cell is capable of reading and writing data; and
when the memory cell operates in the second state, the memory cell is:
capable of retaining previously-written data; and
incapable of reading and writing new data.
10. The method for operating a data processing circuit according to claim 7 , wherein the sampling frequency is selected according to a range of human hearing.
11. A processing system, comprising:
a plurality of selector circuits, wherein each selector circuit is configured to output one of: a first voltage and a second voltage, according to a control signal; and
a plurality of data processing circuits, wherein each data processing circuit is connected to a respective selector circuit, from the plurality of selector circuits, and each data processing circuit comprises a memory cell configured to:
operate in a first state for a pre-defined first time period that is based on a pre-defined sampling frequency; and
operate in a second state for a pre-defined second time period that is based on the pre-defined sampling frequency;
wherein each selector circuit is configured to:
output the first voltage to the memory cell when the memory cell is in the first state; and
output the second voltage to the memory cell when the memory cell is in the second state.
12. The processing system according to claim 11 , further comprising: a voltage generator configured to generate the first voltage and the second voltage.
13. The processing system according to claim 11 , further comprising a clock generator configured to generate a data processor clock signal according to a reference clock signal.
14. The processing system according to claim 13 , wherein the memory cell receives the data processor clock signal.
15. The processing system according to claim 13 , wherein the data processor clock signal has a clock frequency equal to the sampling frequency multiplied by a whole number.
16. The processing system according to claim 15 , wherein the first time period is equal to an inverse of the clock frequency.
17. The processing system according to claim 11 , further comprising a voltage control circuit configured to generate the control signal according to the sampling frequency.
18. The processing system according to claim 11 , wherein:
the first voltage is less than a maximum operating voltage of the memory cell and greater than a minimum operating voltage of the memory cell; and
the second voltage is less than the minimum operating voltage of the memory cell and greater than a minimum retention voltage of the memory cell.
19. The processing system according to claim 11 , wherein the sampling frequency is selected according to a range of human hearing.
20. The processing system according to claim 11 , wherein:
when the memory cell operates in the first state, the memory cell is capable of reading and writing data; and
when the memory cell operates in the second state, the memory cell is:
capable of retaining previously-written data; and
incapable of reading and writing new data.