Low stress asymmetric dual side module
Implementations of semiconductor packages may include a first substrate having two or more die coupled to a first side, a clip coupled to each of the two or more die on the first substrate and a second substrate having two or more die coupled to a first side of the second substrate. A clip may be coupled to each of the two or more die on the second substrate. The package may include a lead frame between the first substrate and the second substrate and a molding compound. A second side of each of the first substrate and the second substrate may be exposed through the molding compound. A perimeter of the first substrate and a perimeter of the second substrate may not fully overlap when coupled through the lead frame.
1. A semiconductor package comprising:
a first substrate comprising two or more die coupled to a first side of the first substrate, wherein a first clip is coupled to each of the two or more die coupled to the first substrate;
a second substrate comprising two or more die coupled to a first side of the second substrate, wherein a second clip is coupled to each of the two or more die coupled to the second substrate;
a lead frame coupled between the first substrate and the second substrate;
a molding compound encapsulating the lead frame wherein a second side of each of the first substrate and the second substrate are exposed through the molding compound; and
wherein a perimeter of the first substrate only partially overlaps a perimeter of the second substrate and the perimeter of the second substrate only partially overlaps the perimeter of the first substrate when the first substrate and second substrate are coupled through the lead frame.
2. The semiconductor package of claim 1 , wherein the lead frame is coupled to the same terminal of the first substrate and of the second substrate.
3. The semiconductor package of claim 1 , wherein the first substrate and the second substrate comprise a direct bonded copper substrate with one of an alumina (Al 2 O 3 ) ceramic doped with zirconium dioxide (ZrO 2 ), a silicon nitride (Si 3 N 4 ) ceramic, an aluminum nitride (AlN) ceramic, a high strength AlN (H—AlN) ceramic, and any combination thereof.
4. The semiconductor package of claim 1 , further comprising a heat sink coupled with one of the second side of the first substrate, the second side of the second substrate, or any combination thereof.
5. The semiconductor package of claim 1 , further comprising one or more leads with a cross sectional shape that provides separation between the first substrate and the second substrate.
6. The semiconductor package of claim 1 , wherein the first substrate and the second substrate comprise one of a direct bonded copper substrate (DBC), an insulated metal substrate technology (IMST) substrate, an active metal bonding (AMB) substrate, or any combination thereof.
7. A semiconductor package comprising:
a lead frame;
a first substrate mechanically and electrically coupled to one or more leads of a first side of the lead frame, the first substrate comprising two or more die on the first side of the first substrate, wherein a first clip is coupled to each of the two or more die on the first side of the first substrate;
a second substrate mechanically and electrically coupled to one or more leads of a second side of the lead frame, the second substrate comprising two or more die on the first side of the second substrate, wherein a second clip is coupled to each of the two or more die on the first side of the second substrate; and
a molding compound encapsulating the first side and the second side of the lead frame;
wherein the first substrate and the second substrate are asymmetrically coupled through the leadframe; and
wherein a perimeter of the first side of the first substrate extends beyond a perimeter of the first side of the second substrate and the perimeter of the first side of the second substrate extends beyond the perimeter of the first side of the first substrate.
8. The semiconductor package of claim 7 , wherein the lead frame is coupled to the same terminal of the first substrate and of the second substrate.
9. The semiconductor package of claim 7 , wherein the first substrate and the second substrate comprise a direct bonded copper substrate with one of an alumina (Al 2 O 3 ) ceramic doped with zirconium dioxide (ZrO 2 ), a silicon nitride (Si 3 N 4 ) ceramic, an aluminum nitride (AlN) ceramic, a high strength AlN (H—AlN) ceramic, and any combination thereof.
10. The semiconductor package of claim 7 , further comprising a heat sink coupled with one of the second side of the first substrate, the second side of the second substrate, or any combination thereof.
11. The semiconductor package of claim 7 , further comprising one or more leads with a cross sectional shape that provides separation between the first substrate and the second substrate.
12. The semiconductor package of claim 7 , wherein the first substrate and the second substrate comprise one of a direct bonded copper substrate (DBC), an insulated metal substrate technology (IMST) substrate, an active metal bonding (AMB) substrate, or any combination thereof.
13. The semiconductor package of claim 5 , wherein the cross sectional shape comprises a C-shape.
14. The semiconductor package of claim 5 , wherein the cross sectional shape comprises an S-shape.
15. The semiconductor package of claim 14 , wherein the one or more leads is directly coupled to a terminal of the first substrate and a terminal of the second substrate and wherein the terminal of the first substrate is aligned with the terminal of the second substrate.
16. The semiconductor package of claim 14 , wherein the one or more leads is directly coupled to a terminal of the first substrate and a terminal of the second substrate and wherein the terminal of the first substrate is misaligned with the terminal of the second substrate.
17. The semiconductor package of claim 11 , wherein the cross sectional shape comprises a C-shape.
18. The semiconductor package of claim 11 , wherein the cross sectional shape comprises an S-shape.
19. The semiconductor package of claim 18 , wherein the one or more leads is directly coupled to a terminal of the first substrate and a terminal of the second substrate and wherein the terminal of the first substrate is aligned with the terminal of the second substrate.
20. The semiconductor package of claim 18 , wherein the one or more leads is directly coupled to a terminal of the first substrate and a terminal of the second substrate and wherein the terminal of the first substrate is misaligned with the terminal of the second substrate.