IP Library Granted Patent US 10,720,725
Granted Patent B2
US 10,720,725 · App. 16/783,345 · Granted Jul 21, 2020

Flexible press fit pins for semiconductor packages and related methods

Inventors: Yushuang Yao (Seremban, MY); Chee Hiong Chew (Seremban, MY); Atapol Prajuckamol (Klaeng, TH)
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
H01R13/05H01R12/57H01R12/585H01R43/02H01R43/16H01L2224/48091H01L2224/48227
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Quick Facts
Patent No.
US 10,720,725
App. No.
16/783,345
Granted
Jul 21, 2020
Kind
B2
Abstract

Implementations of pins for semiconductor packages may include: an upper contact portion having a contact surface coupled with a pin receiver; a lower portion having a vertical stop and at least two curved legs; a horizontal base coupled directly to the at least two curved legs and configured to be soldered to a substrate to mechanically and electrically couple the pin to the substrate, the horizontal base having an upper contact surface, and; a gap between a bottom contact surface of the vertical stop and the upper contact surface of the horizontal base.

Claims (33)

1. A pin for a semiconductor package, comprising:

an upper portion;

a lower portion comprising a single vertical stop, the lower portion further comprising at least two curved portions, each curved portion comprising a c-shape;

a horizontal base coupled directly to the at least two curved portions and configured to be soldered to a substrate to mechanically and electrically couple the pin to the substrate; and

a gap between the single vertical stop and an upper contact surface of the horizontal base.

2. The pin of claim 1 , wherein the single vertical stop is between the at least two curved portions.

3. The pin of claim 1 , wherein the single vertical stop is configured to stop movement of the pin when the single vertical stop contacts the upper contact surface.

4. The pin of claim 1 , wherein the upper portion comprises a deformable portion configured to deform along a direction substantially perpendicular with a longest length of the pin in response to inserting the upper portion into a pin receiver.

5. The pin of claim 1 , wherein the pin comprises a plurality of stops extending substantially perpendicular to a longest length of the pin and configured to prevent the pin from moving relative to a casing of a semiconductor package when the pin is removed from a pin receiver.

6. The pin of claim 1 , wherein a gap is present between curves of the at least two curved portions.

7. The pin of claim 1 , wherein each of the curves of the at least two curved portions are substantially parallel.

8. A pin for a semiconductor package, comprising:

an upper portion;

a lower portion comprising a single vertical stop, the lower portion further comprising at least two curved portions, each curved portion comprising an s-shape;

a horizontal base coupled directly to the at least two curved portions and configured to be soldered to a substrate to mechanically and electrically couple the pin to the substrate; and

a gap between the single vertical stop and an upper contact surface of the horizontal base.

9. The pin of claim 8 , wherein a first section of each of the two curved portions is collinear with a longest length of the pin.

10. The pin of claim 8 , wherein a second section of each of the two curved portions is coupled to the horizontal base through a bend comprising an angle between 60 and 120 degrees.

11. The pin of claim 8 , wherein the at least two curved portions are configured to flex to allow the single vertical stop to move toward the upper contact surface in response to a pressure applied to the pin along a direction collinear with a longest length of the pin toward the upper contact surface.

12. The pin of claim 8 , wherein the at least two curved portions are configured to stop flexing after the at least two curved portions have bent sufficiently to allow the single vertical stop to contact the upper contact surface.

13. The pin of claim 8 , wherein the upper portion comprises a deformable portion configured to deform along a direction substantially perpendicular with a longest length of the pin in response to inserting the upper portion into a pin receiver.

14. The pin of claim 8 , wherein the pin comprises a plurality of stops extending perpendicularly to a longest length of the pin and configured to prevent the pin from moving relative to a casing of a semiconductor package when the pin is removed from a pin receiver.

15. A pin for a semiconductor package, comprising:

an upper portion;

a lower portion comprising a single vertical stop, the lower portion further comprising at least two curved portions, each curved portion comprising one of an s-shape or a c-shape;

a horizontal base coupled directly to the at least two curved portions and configured to be soldered to a substrate to mechanically and electrically couple the pin to the substrate; and

a gap between the single vertical stop and an upper contact surface of the horizontal base;

wherein each of the at least two curved portions further comprise a tapered portion coupled directly with the horizontal base.

16. The pin of claim 15 , wherein the single vertical stop is between the at least two curved portions.

17. The pin of claim 15 , wherein a second portion of each of the at least two curved portions is coupled to the horizontal base through a bend comprising an angle between 60 and 90 degrees.

18. The pin of claim 15 , wherein the single vertical stop is configured to stop movement of the pin when the single vertical stop contacts the upper contact surface.

19. The pin of claim 15 , wherein the upper portion comprises a deformable portion configured to deform along a direction substantially perpendicular with a longest length of the pin in response to inserting the upper portion into a pin receiver.

20. The pin of claim 15 , wherein the pin comprises a plurality of stops extending perpendicularly to a longest length of the pin and configured to prevent the pin from moving relative to a casing of a semiconductor package when the pin is removed from a pin receiver.

Assignments (3)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 052656, FRAME 0842 Recorded Jun 23, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064080/0149 →
SECURITY INTEREST Recorded May 13, 2020
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 052656/0842 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 6, 2020
From: YAO, YUSHUANG; CHEW, CHEE HIONG; PRAJUCKAMOL, ATAPOL
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 051738/0223 →
Continuity (5)
Continuation 16249429 · Jan 16, 2019
Continuation 15443671 · Feb 27, 2017
Continuation 14703002 · May 4, 2015
Provisional Application 62013322 · Jun 17, 2014
Related Publication 20200176907A1 · Jun 4, 2020
Cited By (1)
US 12,249,781