IP Library Granted Patent US 11,282,764
Granted Patent B2
US 11,282,764 · App. 16/784,999 · Granted Mar 22, 2022

Structure and method related to a power module using a hybrid spacer

Inventors: Liangbiao Chen (Scarborough, ME); Yong Liu (Cumberland Foreside, ME); Tzu-Hsuan Cheng (Scarborough, ME); Stephen St. Germain (Gilbert, AZ); Roger Arbuthnot (Mesa, AZ)
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
H01L23/3675H01L21/565H01L23/3107H01L23/3735H01L24/32H05K7/2089H01L2224/32245H01L2224/84801H01L2924/13055
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Quick Facts
Patent No.
US 11,282,764
App. No.
16/784,999
Granted
Mar 22, 2022
Kind
B2
Abstract

A power module includes a spacer block, a thermally conductive substrate coupled to one side of the spacer block, and a semiconductor device die coupled to an opposite side of the spacer block. The spacer block includes a solid spacer block and an adjacent flexible spacer block. An inner portion of the device die is coupled to the solid spacer block, and an outer portion of the semiconductor device die is coupled to the adjacent flexible spacer block.

Claims (37)

1. A module, comprising:

a spacer block including a solid metal spacer block and an adjacent flexible spacer block made of metallic material disposed between two metal layers;

a thermally conductive substrate coupled to a first side of the spacer block;

a semiconductor device die coupled to a second side, opposite the first side, of the spacer block; and

an inner portion of the semiconductor device die being coupled to the solid metal spacer block, and an outer portion of the semiconductor device die being coupled to the adjacent flexible spacer block.

2. The module of claim 1 , wherein the solid metal spacer block provides a thermal pathway for heat flow from the semiconductor device die to the thermally conductive substrate.

3. The module of claim 1 , wherein the adjacent flexible spacer block has a corrugated structure made of a metallic layer.

4. The module of claim 1 , wherein the adjacent flexible spacer block at least partially surrounds the solid metal spacer block.

5. The module of claim 1 , wherein the adjacent flexible spacer block is a strip attached to, and extending from, a side of the solid metal spacer block toward an edge of the semiconductor device die.

6. The module of claim 5 , wherein the adjacent flexible spacer block is coupled to a signal pad region at the edge of the semiconductor device die.

7. The module of claim 1 , wherein the adjacent flexible spacer block has a corrugated structure made of at least one of a straight fin, a tilted fin, a bent fin, a curved fin, or an S-shaped fin.

8. The module of claim 1 , wherein the semiconductor device die includes at least one of a fast recovery diode (FRD) or an insulated gate bipolar transistor (IGBT).

9. A module, comprising:

a spacer block including a solid spacer block and an adjacent flexible spacer block;

a thermally conductive substrate coupled to a first side of the spacer block, the thermally conductive substrate being a direct bonded copper (DBC) substrate,

a semiconductor device die coupled to a second side, opposite the first side, of the spacer block; and

an inner portion of the semiconductor device die being coupled to the solid spacer block, and an outer portion of the semiconductor device die being coupled to the adjacent flexible spacer block.

10. The module of claim 9 , wherein the adjacent flexible spacer block is configured to accommodate mechanical displacement of the semiconductor device die in the module induced by coefficient of thermal expansion (CTE) mismatch.

11. A module, comprising:

a spacer block including a solid spacer block and an adjacent flexible spacer block;

a thermally conductive substrate coupled to a first side of the spacer block;

a semiconductor device die coupled to a second side, opposite the first side, of the spacer block; and

an inner portion of the semiconductor device die being coupled to the solid spacer block, and an outer portion of the semiconductor device die being coupled to the adjacent flexible spacer block, the solid spacer block and the adjacent flexible spacer block are disposed between a plurality of metal layers and fixedly coupled in place between at least two of the plurality of metal layers by solder.

12. A method, comprising:

disposing a flexible spacer block made of metallic material adjacent to a solid metal spacer block on a metal layer;

coupling an inner portion of a semiconductor device die to the solid metal spacer block across the metal layer; and

coupling an edge portion of the semiconductor device die to the flexible spacer block across the metal layer.

13. The method of claim 12 , wherein the disposing the flexible spacer block includes disposing the solid metal spacer block in an opening in the flexible spacer block.

14. The method of claim 12 , wherein the disposing the flexible spacer block includes disposing the flexible spacer block as strip attached to, and extending from, a side of the solid metal spacer block.

15. The method of claim 14 , wherein the coupling the edge portion of the semiconductor device die to the flexible spacer block includes coupling the flexible spacer block to a signal pads region at the edge of the semiconductor device die.

16. The method of claim 14 , wherein the semiconductor device die includes at least one of a fast recovery diode (FRD) or an insulated gate bipolar transistor (IGBT).

17. A module, comprising:

a first device die and a second device die, the first device die having an edge portion including at least one signal pad; and

a spacer block including a solid metal spacer block coupled to a flexible spacer block made of metallic material disposed on a metal layer, the solid metal spacer block being coupled to the first device die and the second device die across the metal layer, the flexible spacer block being coupled across the metal layer to the edge portion including the at least one signal pad.

18. The module of claim 17 , wherein the solid metal spacer block includes a first sub-block coupled to the first device die and a second sub-block coupled to the second device die, and the flexible spacer block at least partially surrounds the first sub-block and at least partially surrounds the second sub-block.

19. The module of claim 18 , wherein the flexible spacer block coupled to the edge portion of the first device die extends away continuously from the edge portion to at least partially surround the first sub-block and at least partially surround the second sub-block.

20. The module of claim 17 , wherein the first device die includes an insulated gate bipolar transistor (IGBT).

Assignments (3)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 052656, FRAME 0842 Recorded Jun 23, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064080/0149 →
SECURITY INTEREST Recorded May 13, 2020
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 052656/0842 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 7, 2020
From: CHEN, LIANGBIAO; LIU, YONG; CHENG, TZU-HSUAN; ST. GERMAIN, STEPHEN; ARBUTHNOT, ROGER
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 051754/0362 →
Continuity (1)
Related Publication 20210249329A1 · Aug 12, 2021