Methods and apparatus for an encoder
Various embodiments of the present technology comprise a method and apparatus for an encoder. In various embodiments, the encoder is configured to perform offset and gain correction. The encoder includes a first correction circuit to perform offset and gain correction and a second correction circuit to perform additional offset and gain correction.
1. An encoder capable of receiving first channel data and second channel data, comprising:
a first circuit comprising:
a plurality of variable gain amplifiers configured to:
apply a first gain to the first channel data and the second channel data; and
apply a first DC offset correction to the first channel data and the second channel data; and
a second circuit connected to an output terminal of the first circuit, and comprising:
an offset correction circuit configured to:
apply a second DC offset correction to the first channel data and the second channel data; and
generate:
first corrected data based on the first channel data; and
second corrected data based on the second channel data; and
a gain correction circuit coupled to the offset correction circuit, and configured to apply a second gain to the first corrected data and the second corrected data according to a predetermined ideal signal having a phase error of substantially zero between the first channel data and the second channel data.
2. The encoder according to claim 1 , wherein the second circuit further comprises a peak and valley detection circuit configured to compute a peak and a valley of each of the first and second channel data.
3. The encoder according to claim 2 , wherein the peak and valley detection circuit, the offset correction circuit and the gain correction circuit are connected in series.
4. The encoder according to claim 1 , wherein the first gain is a fixed gain and the second gain is a dynamic gain.
5. The encoder according to claim 1 , wherein:
the first DC offset correction comprises a coarse correction; and
the second DC offset correction comprises a fine correction.
6. The encoder according to claim 1 , wherein the second circuit is further configured to:
generate a first comparator signal according to the first channel data; and
generate a second comparator signal according to the second channel data.
7. The encoder according to claim 1 , wherein the plurality of variable gain amplifiers comprises:
a first set of series-connected amplifiers;
a second set of series-connected amplifiers to receive the second channel data.
8. The encoder according to claim 7 , wherein the first set of series-connected amplifiers applies the first gain and first DC offset correction to the first channel data; and the second set of series-connected amplifiers applies the second gain and the second DC offset correction to the second channel data.
9. A method for gain and offset correction of first channel data and second channel data, comprising:
applying a first gain to the first channel data and the second channel data;
applying a first DC offset correction to the first channel data and the second channel data;
converting the first channel data to a first digital signal and converting the second channel data to a second digital signal;
apply a second DC offset correction to the first and second digital signals;
generating corrected first and second digital signals; and
applying a second gain to the corrected first and second digital signals according to a predetermined ideal signal having a phase error of substantially zero between the first channel data and the second channel data.
10. The method according to claim 9 , further comprising computing a peak and a valley of each of the first and second channel data.
11. The method according to claim 10 , computing the second DC offset based on the computed peak and compute valley.
12. The method according to claim 9 , wherein:
the first gain is a fixed gain;
the second gain is a dynamic gain;
the first DC offset correction is a coarse correction; and
the second DC offset correction is a fine correction.
13. A system comprising:
a motor assembly connected to a drive circuit, wherein the motor assembly comprises:
a motor capable of generating first channel data and second channel data; and
an encoder positioned adjacent to the motor and configured to monitor the motor; wherein the encoder comprises:
a first correction circuit configured to:
apply a first gain to the first channel data and the second channel data; and
apply a first DC offset correction to the first channel data and the second channel data;
generate a first comparator signal according to the first channel data; and
generate a second comparator signal according to the second channel data;
a signal conversion circuit connected to the first correction circuit and configured to convert the first channel data into a first digital signal and the second channel data into a second digital signal;
a second correction circuit connected in series with the signal conversion circuit and configured to:
apply a second DC offset correction to the first and second digital signals; and
generate corrected first and second digital signals; and
apply a second gain to the corrected first and second digital signals according to a predetermined ideal signal; and
a signal processing circuit connected to the second correction circuit and configured to compute a phase of the motor according to the first comparator signal, the second comparator signal, and the corrected first and second digital signals.
14. The system according to claim 13 , wherein the second correction circuit comprises:
an offset correction circuit configured to:
apply a second DC offset correction to the first channel data and the second channel data; and
generate:
first corrected data based on the first channel data; and
second corrected data based on the second channel data; and
a gain correction circuit coupled to the offset correction circuit, and configured to apply a second gain to the first corrected data and the second corrected data according to a predetermined ideal signal.
15. The system according to claim 13 , wherein the second correction circuit further comprises a peak and valley detection circuit configured to compute a peak and a valley of each of the first and second channel data.
16. The system according to claim 15 , wherein the peak and valley detection circuit, the offset correction circuit, and the gain correction circuit are connected in series.
17. The system according to claim 13 , wherein the first gain is a fixed gain and the second gain is a dynamic gain.
18. The system according to claim 13 , wherein:
the first DC offset correction comprises a coarse correction; and
the second DC offset correction comprises a fine correction.
19. The system according to claim 13 , wherein the first correction circuit, the signal conversion circuit, the second correction circuit, and the signal processing circuit are connected in series.
20. The system according to claim 13 , wherein the first correction circuit comprises:
a first set of series-connected amplifiers to apply the first gain and first DC offset correction to the first channel data; and
a second set of series-connected amplifiers to apply the second gain and the second DC offset correction to the second channel data.