Methods and apparatus for an encoder

1. An integrated circuit capable of receiving a first input signal and a second input signal, comprising:

a first filter configured to compute a first quadrature of the first input signal;

a second filter configured to compute a second quadrature of the second input signal;

a first phase estimation circuit coupled to an output terminal of the first filter and configured to estimate a first phase according to the first input signal and the first quadrature;

a second phase estimation circuit coupled to an output terminal of the second filter and configured to estimate a second phase according to the second input signal and the second quadrature; and

a phase offset circuit coupled to the output terminals of the first and second phase estimation circuits and configured to compute a phase offset based on the first and second phases.

2. The integrated circuit according to claim 1 , further comprising a first correction circuit configured to:

apply a fixed gain to a third input signal and a fourth input signal; and

apply a coarse DC offset correction to the third and fourth input signals;

wherein the first correction circuit generates the first and second input signals according to the third and fourth input signals.

3. The integrated circuit according to claim 1 , further comprising a second correction circuit configured to:

apply a dynamic gain to a third input signal and a fourth input signal; and

apply a fine DC offset correction to the third and fourth input signals;

wherein the second correction circuit generates the first and second input signals according to the third and fourth input signals.

4. The integrated circuit according to claim 3 , wherein the second correction circuit comprises:

a peak and valley detection circuit configured to compute a peak and a valley of each of the third and fourth input signals;

an offset correction circuit coupled to the peak and valley detection circuit and configured to apply the fine DC offset correction; and

a gain correction circuit coupled to the offset correction circuit, and configured to apply the dynamic gain according to an ideal peak signal.

5. The integrated circuit according to claim 1 , further comprising a decimator configured to change a sampling rate of the first and second input signal.

6. The integrated circuit according to claim 1 , wherein:

the first and second phase estimation circuits utilize a Coordinate Rotation Digital Computer (CORDIC) algorithm to compute the first and second phases; and

each of the first and second filters comprise Discrete Hilbert Transform filters.

7. The integrated circuit according to claim 1 , further comprising:

a first delay circuit coupled in parallel with the first filter and configured to apply a time delay to the first input signal; and

a second delay circuit coupled in parallel with the second filter and configured to apply the time delay to the second input signal.

8. The integrated circuit according to claim 1 , computing a final phase according to the phase offset, the first phase, and a frequency.

9. The integrated circuit according to claim 8 , wherein the integrated circuit is further configured to compute a motor position according to the final phase.

10. A method for computing a motor position, comprising: decimating a first input signal and a second input signal; computing a first quadrature of the first signal; computing a second quadrature of the second input signal; computing a first phase according to the first quadrature; computing a second phase according to the second quadrature; computing a phase offset based on the computed first and second phases; and computing the motor position based on the phase offset, the first phase, and a frequency.

11. The method according to claim 10 , further comprising applying a time delay to each of the first and second input signals.

12. The method according to claim 10 , further comprising computing a frequency of the first input signal based on zero crossings and decimating the first and second input signals according to the computed frequency.

13. The method according to claim 10 , further comprising removing a time delay from the phase offset.

14. A system capable of generating a first signal and a second signal, comprising:

a motor assembly comprising:

a motor having a motor position; and

an optical encoder coupled to the motor and comprising:

a first correction circuit configured to:

apply a first gain to the first and second signals;

apply a first DC offset correction to the first and second signals;

generate first channel data; and

generate second channel data;

a second correction circuit coupled to an output terminal of the first correction circuit and configured to:

apply a second gain to the first and second channel data;

apply a second DC offset correction to the first and second channel data;

generate corrected first channel data; and

generate corrected second channel data;

a signal processing circuit coupled to the second correction circuit and configured to:

compute a first quadrature of the corrected first channel data;

compute a second quadrature of the corrected second channel data;

estimate a first phase according to the first signal corrected first channel data and the first quadrature;

estimate a second phase according to the corrected second channel data and the second quadrature; and

compute a phase offset based on the first and second phases.

15. The system according to claim 14 , wherein:

the first gain comprises a fixed gain; and

the second gain comprises a dynamic gain.

16. The system according to claim 14 , wherein:

the first DC offset correction comprises a coarse correction; and

the second DC offset correction comprises a fine correction.

17. The system according to claim 14 , wherein the optical encoder circuit further comprises a decimator coupled between the output terminal of the second correction circuit and the signal processing circuit, and configured to change a sampling rate of the first and second channel data.

18. The system according to claim 14 , wherein the system is further configured to compute:

a final phase according to the phase offset, the first phase, and a frequency; and

the motor position according to the final phase.

19. The system according to claim 14 , wherein the second correction circuit comprises:

a peak and valley detection circuit configured to compute a peak and a valley of each of the first and second channel data;

an offset correction circuit coupled the peak and valley detection circuit and configured to apply the second DC offset correction; and

a gain correction circuit coupled to the offset correction circuit, and configured to apply the second gain correction according to an ideal peak signal.