IP Library Granted Patent US 11,853,245
Granted Patent B2
US 11,853,245 · App. 16/896,122 · Granted Dec 26, 2023

Computing system framework and method for configuration thereof

Inventor: Daniel Davies (Palo Alto, CA)
Assignee: XEROX CORPORATION
G06F13/4022G06F13/4265G06F15/17362
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Quick Facts
Patent No.
US 11,853,245
App. No.
16/896,122
Granted
Dec 26, 2023
Kind
B2
Abstract

A computing system framework and method for configuration thereof are provided. A plurality of processing modules are accessed. Each processing module includes a plurality of processing nodes and each processing node is associated with an intra-module port and an inter-module port. A plurality of intra-module networks are formed. Each intra-module network includes connections between at least a portion of the processing nodes in one of the processing modules via the associated intra-module ports. An enclosed shape of the processing modules is formed by connecting at one inter-module port on each processing module to one inter-module port on an adjacent processing modules. A cable is linked between one of the inter-module ports of one processing module of the enclosed shape to an inter-module port of another processing module of a different group of interconnected processing modules.

Claims (37)

1. A computing system framework, comprising:

a plurality of processing modules, each processing module comprising a plurality of processing nodes and each processing node associated with an intra-module port and an inter-module port;

a plurality of intra-module networks, each intra-module network comprising connections between at least a portion of the processing nodes in one of the processing modules via the associated intra-module ports;

a closed shape of the processing modules represented as M processing modules and formed by connecting at least one inter-module port on each processing module to one inter-module port on an adjacent processing module;

a network switch;

an inter-module network configured to form two or more connections between the closed shape of the processing modules and the network switch, each connection comprising at least one of:

a connection between the network switch and one of the processing modules N on the closed shape and another processing module N+S on the closed shape, by connecting one unused inter-module port on the processing module N to the switch and by connecting another unused inter-module port on the processing module N+S to the network switch, wherein S is an integer divisor of M, N is [x, x+S, . . . , x+(M−S), increment by S], and xis [1, 2, . . . , S−1];

a connection between the network switch and one of the processing modules N on the closed shape and another processing module N+S−1 on the closed shape, by connecting one unused inter-module port on the processing module N to the network switch and by connecting another unused inter-module port on the processing module N+S−1 the network switch, wherein S is an integer divisor of M, N is [x, x+S, . . . , x+(M−S), increment by S], x is [1, 2, . . . , S−1]; and

a connection between the network switch and one of the processing modules N on the closed shape and another processing module N+S−r on the closed shape, by connecting one unused inter-module port on the processing module N to the network switch and by connecting another unused inter-module port on the processing module N+S−r to the network switch, wherein S is an integer divisor of M, N is [x, x+S, . . . , x+(M−S), increment by S], x is [1, 2, . . . , S−1], and r is [2, 3, . . . , S−1]; and

a cable linked between one of the inter-module ports of one processing module of the closed shape to an inter-module port of another processing module of a different group of interconnected processing modules, wherein the different group of interconnected processing module has a configuration that is same or different than the closed shape.

2. A computing system framework according to claim 1 , wherein each processing node is selected from the group comprising:

a processing element, a memory controller, a memory, a storage controller, a storage device, interfaces to intra-module and inter-module ports, and a virtual node.

3. A computing system framework according to claim 1 , wherein the closed shape comprises one of a bus, a ring, a star, a mesh, and a crossbar switch.

4. A computing system framework according to claim 1 , further comprising:

a transmission module to transfer the data packets from one of the processing nodes to another one of the processing nodes via the connections.

5. A computing system framework according to claim 4 , further comprising:

a monitoring module measuring a pattern of the data packet traffic; and

a modification module to amend the connections based upon the packet traffic pattern.

6. A computing system framework according to claim 1 , wherein the network switch is arranged in a center of the closed shape of processing modules.

7. A method for constructing a computing system framework, comprising:

accessing a plurality of processing modules, each processing module comprising a plurality of processing nodes and each processing node associated with an intra-module port and an inter-module port;

within each of one or more of the processing modules, connecting at least a portion of the processing nodes in that processing module via the associated intra-module ports;

forming a closed shape of the processing modules represented as M processing modules by connecting at least one inter-module port on each processing module to one inter-module port on an adjacent processing module;

forming two or more connections around between the closed shape and a network switch, comprising at least one of:

a connection between the network switch and one of the processing modules N on the closed shape and another processing module N+S on the closed shape, by connecting one unused inter-module port on the processing module N to the network switch and by connecting another unused inter-module port on the processing module N+S to the network switch, wherein S is an integer divisor of M, N is [x, x+S, . . . , x+(M−S), increment by S], and x is [1, 2, . . . , S−1];

a connection between the network switch and one of the processing modules N on the closed shape and another processing module N+S−1 on the closed shape, by connecting one unused inter-module port on the processing module N to the network switch and by connecting another unused inter-module port on the processing module N+S−1 to the network switch, wherein S is an integer divisor of M, N is [x, x+S, . . . , x+(M−S), increment by S], x is [1, 2, . . . , S−1]; and

a connection between the network switch and one of the processing modules N on the closed shape and another processing module N+S−r on the closed shape, by connecting one unused inter-module port on the processing module N to the network switch and by connecting another unused inter-module port on the processing module N+S−r to the network switch, wherein S is an integer divisor of M, N is [x, x+S, . . . , x+(M−S), increment by S], x is [1, 2, . . . , S−1], and r is [2, 3, . . . , S−1]; and

linking a cable between one of the inter-module ports of one processing module of the closed shape to an inter-module port of another processing module of a different group of interconnected processing modules, wherein the different group of interconnected processing module has a configuration that is same or different than the closed shape.

8. A method according to claim 7 , wherein each processing node is selected from the group comprising:

a processing element, a memory controller, a memory, a storage controller, a storage device, interfaces to intra-module and inter-module ports, and a virtual node.

9. A method according to claim 7 , wherein the closed shape comprises one of a bus, a ring, a star, a mesh, and a crossbar switch.

10. A method according to claim 7 , further comprising:

transferring the data packets from one of the processing nodes to another one of the processing nodes via the connections.

11. A method according to claim 10 , further comprising:

measuring a pattern of the data packet traffic; and

amending the connections based upon the packet traffic pattern.

12. A method according to claim 7 , wherein the network switch is arranged in a center of the closed shape of processing modules.

Assignments (7)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 14, 2025
From: XEROX CORPORATION
To: GENESEE VALLEY INNOVATIONS, LLC
Reel/Frame 073562/0677 →
SECOND LIEN NOTES PATENT SECURITY AGREEMENT Recorded Jul 2, 2025
From: XEROX CORPORATION
To: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 071785/0550 →
FIRST LIEN NOTES PATENT SECURITY AGREEMENT Recorded Apr 11, 2025
From: XEROX CORPORATION
To: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 070824/0001 →
SECURITY INTEREST Recorded Feb 13, 2024
From: XEROX CORPORATION
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 066741/0001 →
SECURITY INTEREST Recorded Nov 20, 2023
From: XEROX CORPORATION
To: JEFFERIES FINANCE LLC, AS COLLATERAL AGENT
Reel/Frame 065628/0019 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVAL OF US PATENTS 9356603, 10026651, 10626048 AND INCLUSION OF US PATENT 7167871 PREVIOUSLY RECORDED ON REEL 064038 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Jun 28, 2023
From: PALO ALTO RESEARCH CENTER INCORPORATED
To: XEROX CORPORATION
Reel/Frame 064161/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 20, 2023
From: PALO ALTO RESEARCH CENTER INCORPORATED
To: XEROX CORPORATION
Reel/Frame 064038/0001 →
Continuity (5)
Continuation 15990772 · May 28, 2018
Continuation 15645883 · Jul 10, 2017
Continuation 14512341 · Oct 10, 2014
Continuation In Part 14313922 · Jun 24, 2014
Related Publication 20200301865A1 · Sep 24, 2020