Methods and apparatus for variable capacitance detection

1. A sensing circuit, comprising:

an input terminal capable of receiving an input signal;

a sub-circuit connected to the input terminal and configured to generate an output signal at an output terminal, wherein the sub-circuit comprises an inverter;

a logic circuit connected to the output terminal and configured to generate a first control signal and a second control signal according to a reference clock signal;

a first switch connected to the inverter and responsive to the first control signal; and

a second switch connected to the inverter and responsive to the second control signal;

wherein the logic circuit is configured to:

measure a total time period, wherein the total time period comprises:

a first period defined according to the first control signal and the output signal; and

a second period defined according to the second control signal and the output signal, wherein the second period is later in time than the first period; and

compute a capacitance value based on the total time period, wherein the capacitance value is directly proportional to the total time period.

2. The sensing circuit according to claim 1 , wherein the first period is defined by a start point marked by a rising edge of the first control signal and an end point marked by a transition edge of the output signal.

3. The sensing circuit according to claim 1 , wherein the second period is defined by a start point marked by a rising edge of the second control signal and an end point marked by a transition edge of the output signal.

4. The sensing circuit according to claim 1 , further comprising an RC oscillator connected to the logic circuit and configured to generate the reference clock signal.

5. The sensing circuit according to claim 1 , wherein the input signal is inversely proportional to a capacitance value.

6. The sensing circuit according to claim 1 , wherein the first period is defined by a start point marked by enabling the first switch and an end point marked by a transition of the output signal.

7. The sensing circuit according to claim 1 , wherein the second period is defined by a start point marked by enabling the second switch and an end point marked by a transition of the output signal.

8. The sensing circuit according to claim 1 , wherein, during the first period, the input signal is increasing in value and the output signal transitions from a low value to a high value when the input signal equals a threshold voltage of the inverter.

9. The sensing circuit according to claim 1 , wherein, during the second period, the input signal is decreasing in value and the output signal transitions from a high value to a low value when the input signal equals a threshold voltage of the inverter.

10. A method for computing a capacitance value using a sensing circuit having an inverter, comprising:

receiving an input voltage at an input terminal of the inverter;

generating an output signal with the inverter, wherein the output signal is based on the input voltage;

generating a first event defined by a transition edge of a first control signal, wherein the first control signal controls operation of the inverter;

identifying a second event defined by a transition edge of the output signal;

measuring a total time period, wherein a starting point of the total time period is based on the first event and an ending point of the total time period is coincident with the second event; and

computing the capacitance value based on the total time period, wherein the capacitance value is directly proportional to the total time period.

11. The method according to claim 10 , wherein the total time period comprises:

a first period defined by a start point marked by a rising edge of the first control signal and an end point marked by a rising edge of the output signal; and

a second period defined by a start point marked by a rising edge of the second control signal value and a falling edge of the output signal.

12. The method according to claim 11 , wherein, during the first period, the input signal is increasing in value and the output signal transitions from a low value to a high value when the input signal equals a threshold voltage of the inverter.

13. The method according to claim 11 , wherein, during the second period, the input signal is decreasing in value and the output signal transitions from a high value to a low value when the input signal equals a threshold voltage of the inverter.

14. The method according to claim 10 , wherein:

the starting point of the total time period is coincident with the first event; and measuring the total time period is intermittent.

15. The method according to claim 10 , wherein:

the starting point of the total time period is later in time than the first event; and measuring the total time period is continuous.

16. A system, comprising:

a pressure sensor circuit for detecting pressure, wherein a capacitance of the pressure sensor varies according to the detected pressure; and

a sensing circuit connected to the pressure sensor circuit and configured to sense an input voltage that is inversely proportional to the capacitance, wherein the sensing circuit comprises:

a plurality of inverters connected in series with each other and configured to generate an output signal at an output terminal according to the input voltage;

a clock generator configured to generate a reference clock signal;

a logic circuit connected to the output terminal and configured to generate a first control signal and a second control signal according to the reference clock signal, wherein the first and second control signals control operation of the plurality of inverters;

wherein the logic circuit is configured to:

measure a total time period, wherein a starting point of the total time period is based on the first control signal and an ending point of the total time period is coincident with a transition edge of the output signal; and

compute the capacitance based on the total time period, wherein the capacitance is directly proportional to the total time period.

17. The system according to claim 16 , wherein the total time period is measured according to a first period defined by a start point marked by a rising edge of the first control signal and an end point marked by a rising edge of the output signal.

18. The system according to claim 17 , wherein the starting point of the total time period is coincident with the rising edge of the first control signal.

19. The system according to claim 17 , wherein the starting point of the total time period is later in time than the rising edge of the first control signal by a multiple of the reference clock signal.

20. The system according to claim 16 , wherein the total time period is measured according to a second period defined by a start point marked by a rising edge of the second control signal value and an end point marked by a falling edge of the output signal.