IP Library Granted Patent US 11,481,532
Granted Patent B2
US 11,481,532 · App. 17/076,039 · Granted Oct 25, 2022

Systems and methods for designing a discrete device product

Inventors: James Joseph Victory (Trabuco Canyon, CA); Thomas Neyer (Munich, DE); YunPeng Xiao (Shanghai, CN); Hyeongwoo Jang (Bucheon-Si, KR); Peter Dingenen (Oudenaarde, BE); Vaclav Valenta (Brno, CZ); Tirthajyoti Sarkar (Fremont, CA); Mehrdad Baghaie Yazdi (Munich, DE); Christopher Lawrence Rexer (Scottsdale, AZ); Stanley Benczkowski (Bear Creek Township, PA); Thierry Bordignon (Toulouse, FR); Wai Lun Chu (Kowloon, HK); Roman Sickaruk (Nezamyslice, CZ)
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
G06F30/31G06F30/367G06F30/392G06F30/398G06N3/04G06N3/08G06F2111/02G06F2117/12G06F2119/08
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Quick Facts
Patent No.
US 11,481,532
App. No.
17/076,039
Granted
Oct 25, 2022
Kind
B2
Abstract

Implementations disclosed herein may include receiving from a user a selection of at least one die, a package type, and at least one test condition; generating, using a processor, a product die configuration and a product package configuration using a predictive modeling module and the at least one die and the package type; generating a graphic design system file; generating a package bonding diagram; generating a product spice model of the discrete device product using a technology computer aided design module; generating, using a processor, one or more datasheet characteristics of the discrete device product with the product SPICE model; generating a product datasheet for the discrete device product using the graphic design system file; and using a second interface generated by a computing device to provide access to the graphic design system file, the package bonding diagram, the product datasheet, and the product SPICE model.

Claims (37)

1. A system configured for designing a discrete device product, the system comprising:

one or more hardware processors configured by machine-readable instructions to:

use a first interface generated by a computing device, receive from a user a selection of at least one discrete device die and a selection of at least one test condition;

generate, using the one or more processors, a product die configuration using the at least one discrete device die and a predictive modeling module comprising a back propagated model generated by a neural network trained using data from previous discrete device products;

generate, using the one or more processors, a graphic design system file using a graphic design system module with the product die configuration;

generate, using the one or more processors, a package bonding diagram using a build diagram system module with the graphic design system file;

generate, using the one or more processors, a product SPICE model corresponding with the product die configuration with a product SPICE model generating module;

provide, using the one or more processors, the product SPICE model to a product simulation module;

generate, using the one or more processors, one or more datasheet characteristics of the discrete device product with the product SPICE model using the product simulation module;

provide, using the one or more processors, the one or more datasheet characteristics to a datasheet formation module;

generate, using the one or more processors, product datasheet for the discrete device product using the graphic design system file, the package bonding diagram, and the one or more datasheet characteristics; and

using a second interface generated by a computing device, provide access to the graphic design system file, the package bonding diagram, the product SPICE model, and the product datasheet to the user.

2. The system of claim 1 , where the system is further configured to: receive a selection of a package type, include the package in the product die configuration, select a die SPICE model corresponding with the at least one discrete device die, and select a package SPICE model corresponding with the package type for generating the product SPICE model with the product SPICE model generating module.

3. The system of claim 1 , wherein the back propagated model is used to predict one or more electrical performance parameters of the discrete device product.

4. The system of claim 1 , wherein the back propagated model is used to predict a die dimension, gate pad location, or gate runner.

5. The system of claim 1 , wherein the neural network comprises two input neurons, three densely connected hidden layers comprising rectified linear network unit neurons, and an output layer of linearly activated neurons.

6. The system of claim 1 , wherein the graphic design system module uses a native parameterized layout cell (PCELL).

7. The system of claim 1 , wherein the graphic design system module uses a generic parameterized layout cell (PCELL).

8. The system of claim 1 , wherein the build diagram system module uses a virtual clip to generate the package bonding diagram.

9. A method of designing a discrete device product, the method comprising:

using a first interface generated by a computing device, receiving from a user a selection of at least one discrete device die and a selection of at least one test condition;

generating, using a processor, a product die configuration and a product package configuration using a predictive modeling module and the at least one discrete device die, the predictive modeling module comprising a back propagated model generated by a neural network trained using data from previous discrete device products;

generating, using the processor, a graphic design system file using a graphic design system module with the product die configuration;

generating, using the processor, a package bonding diagram using a build diagram system module with the graphic design system file;

generating, using the processor, a product SPICE model corresponding with the product die configuration using a product SPICE model generating module;

providing, using the processor, the product SPICE model to a product simulation module;

generating, using the processor, one or more datasheet characteristics of the discrete device product with the product SPICE model;

providing, using the processor, the one or more datasheet characteristics to a datasheet formation module;

generating, using the processor, a product datasheet for the discrete device product using the graphic design system file, the package bonding diagram, and the one or more datasheet characteristics; and

using a second interface generated by a computing device, providing access to the graphic design system file, the package bonding diagram, the package SPICE model, and the product datasheet to the user.

10. The method of claim 9 , further comprising: receiving a selection of a package type, including the package in the product die configuration, selecting a die SPICE model corresponding with the at least one discrete device die, and selecting a package SPICE model corresponding with the package type for generating the product SPICE model with the product SPICE model generating module.

11. The method of claim 9 , wherein the back propagated model is used to predict one or more electrical performance parameters of the discrete device product.

12. The method of claim 9 , wherein the back propagated model is used to predict a die dimension, gate pad location, or gate runner.

13. The method of claim 9 , wherein the neural network comprises two input neurons, three densely connected hidden layers comprising rectified linear network unit neurons, and an output layer of linearly activated neurons.

14. The method of claim 9 , wherein the graphic design system module uses a native parameterized layout cell (PCELL).

15. The method of claim 9 , wherein the graphic design system module uses a generic parameterized layout cell (PCELL).

16. The method of claim 9 , wherein the build diagram system module uses a virtual clip to generate the package bonding diagram.

Assignments (1)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL 055315, FRAME 0350 Recorded Aug 17, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064618/0881 →