Semiconductor devices with single-photon avalanche diodes and isolation structures
An imaging device may include single-photon avalanche diodes (SPADs). To mitigate crosstalk, isolation structures may be formed around each SPAD. The isolation structures may include front side deep trench isolation structures that extend partially or fully through a semiconductor substrate for the SPADs. The isolation structures may include a metal filler such as tungsten that absorbs photons. The isolation structures may include a p-type doped semiconductor liner to mitigate dark current. The isolation structures may include a buffer layer such as silicon dioxide that is interposed between the metal filler and the p-type doped semiconductor liner. The isolation structures may have a tapered portion or may be formed in two steps such that the isolation structures have different portions with different properties. An additional filler such as polysilicon or borophosphosilicate glass may be included in some of the isolation structures in addition to the metal filler.
1. A semiconductor device comprising:
a substrate;
a single-photon avalanche diode formed in the substrate; and
a front side deep trench isolation structure in the substrate that is interposed between the single-photon avalanche diode and an adjacent single-photon avalanche diode, wherein the front side deep trench isolation structure comprises a metal filler in a trench, wherein the trench has a p-type doped semiconductor liner, wherein the p-type doped semiconductor liner has a first doping concentration in a first portion of the front side deep trench isolation structure and a second doping concentration that is different than the first doping concentration in a second portion of the front side deep trench isolation structure.
2. The semiconductor device defined in claim 1 , wherein the front side deep trench isolation structure extends completely through the substrate from a front surface of the substrate to a back surface of the substrate.
3. The semiconductor device defined in claim 2 , wherein the metal filler has a depth in the substrate that is less than a total thickness of the substrate.
4. The semiconductor device defined in claim 3 , wherein the a first portion has a first width and the second portion has a second width that is different than the first width.
5. The semiconductor device defined in claim 4 , wherein the first portion is adjacent the back surface of the substrate, wherein the second portion is adjacent the front surface of the substrate, wherein the first width is less than the second width, and wherein the first doping concentration is less than the second doping concentration.
6. The semiconductor device defined in claim 5 , wherein the metal filler is formed in the second portion but not the first portion.
7. The semiconductor device defined in claim 3 , wherein the front side deep trench isolation structure includes a buffer layer that is interposed between the metal filler and the substrate.
8. The semiconductor device defined in claim 2 , wherein the metal filler partially fills the trench and wherein an additional filler partially fills the trench.
9. The semiconductor device defined in claim 8 , wherein the metal filler and the additional filler have an interface, wherein the metal filler is formed between the front surface of the substrate and the interface, and wherein the additional filler is formed between a back surface of the substrate and the interface.
10. The semiconductor device defined in claim 1 , wherein the front side deep trench isolation structure extends through the substrate from a front surface of the substrate towards a back surface of the substrate and wherein the front side deep trench isolation structure does not extend completely through the substrate.
11. The semiconductor device defined in claim 10 , wherein the front side deep trench isolation structure includes a buffer layer that is interposed between the metal filler and the p-type doped semiconductor liner.
12. The semiconductor device defined in claim 11 , wherein the buffer layer comprises silicon dioxide.
13. The semiconductor device defined in claim 1 , further comprising:
a p-type doped region in the substrate that is biased to an anode voltage, wherein the p-type doped semiconductor liner is electrically connected to the p-type doped region, and wherein the p-type doped semiconductor liner and the p-type doped region collectively serve as an anode contact for the single-photon avalanche diode.
14. A semiconductor device comprising:
a substrate;
a single-photon avalanche diode formed in the substrate; and
a front side deep trench isolation structure in the substrate that is interposed between the single-photon avalanche diode and an adjacent single-photon avalanche diode, wherein the front side deep trench isolation structure comprises a metal filler in a trench, wherein the trench has a p-type doped semiconductor liner, wherein the front side deep trench isolation structure includes a buffer layer that is interposed between the metal filler and the substrate, wherein the trench has a tapered portion adjacent to a front surface of the substrate, wherein no metal filler is formed in the tapered portion, and wherein a material that is used to form the buffer layer is formed in the tapered portion.
15. The semiconductor device defined in claim 14 , wherein the front side deep trench isolation structure extends completely through the substrate from a front surface of the substrate to a back surface of the substrate.
16. A semiconductor device comprising:
a substrate;
a single-photon avalanche diode formed in the substrate; and
a front side deep trench isolation structure in the substrate that is interposed between the single-photon avalanche diode and an adjacent single-photon avalanche diode, wherein the front side deep trench isolation structure comprises a metal filler and an additional filler in a trench, wherein the trench has a p-type doped semiconductor liner, wherein the additional filler comprises a material selected from the group consisting of: polysilicon and borophosphosilicate glass.
17. The semiconductor device defined in claim 16 , wherein the front side deep trench isolation structure extends completely through the substrate from a front surface of the substrate to a back surface of the substrate.
18. The semiconductor device defined in claim 16 , wherein the front side deep trench isolation structure extends through the substrate from a front surface of the substrate towards a back surface of the substrate and wherein the front side deep trench isolation structure does not extend completely through the substrate.
19. The semiconductor device defined in claim 16 , wherein the front side deep trench isolation structure includes a buffer layer that is interposed between the metal filler and the p-type doped semiconductor liner.
20. The semiconductor device defined in claim 19 , wherein the buffer layer comprises silicon dioxide.