Semiconductor device with backmetal and related methods

1. A semiconductor device comprising:

a die comprising a first side and a second side;

a contact pad coupled to the first side of the die;

a metal layer coupled to the second side of the die; and

a mold compound coupled directly to the metal layer;

wherein an outer sidewall of the mold compound comprises a step facing away from the metal layer;

wherein a thickness of the die is less than 30 micrometers;

wherein the contact pad is exposed through a passivation layer coupled over the die;

wherein the die is a singulated die;

wherein the mold compound covers and contacts an outermost sidewall of the metal layer;

wherein an outer sidewall of the die is coplanar with an outermost sidewall of the mold compound; and

wherein a perimeter of an entirety of the metal layer is less than and lies within a perimeter of the die.

2. The device of claim 1 , wherein the thickness of the die is substantially the same as the thickness of the metal layer.

3. The device of claim 1 , wherein five sides of the metal layer are covered by the mold compound and wherein an entire surface of the metal layer opposite a surface facing the die lies in the same plane.

4. The device of claim 1 , wherein the mold compound is directly coupled over the metal layer.

5. The semiconductor device of claim 1 , wherein a surface of the contact pad facing away from the die is coplanar with a surface of a passivation layer facing away from the die.

6. A semiconductor device comprising:

a die comprising a first side and a second side;

a contact pad coupled to the first side of the die;

a metal layer coupled to the second side of the die; and

a mold compound directly coupled to and over an entire first surface of the metal layer opposite a second surface of the metal layer facing the second side of the die;

wherein an outer sidewall of the mold compound comprises a step;

wherein the die is singulated from a wafer;

wherein the mold compound covers and contacts an outermost sidewall of the metal layer;

wherein an outer sidewall of the die is coplanar with an outermost sidewall of the mold compound; and

wherein a perimeter of an entirety of the metal layer is less than and lies within a perimeter of the die.

7. The device of claim 6 , wherein a thickness of the die is substantially the same as a thickness of the metal layer.

8. The device of claim 6 , wherein a thickness of the die is no more than four times a thickness of the metal layer.

9. The device of claim 6 , wherein the step surrounds an outermost sidewall of the metal layer.

10. The semiconductor wafer of claim 6 , wherein a surface of the contact pad facing away from the die is coplanar with a surface of a passivation layer facing away from the die.

11. A semiconductor wafer comprising:

a wafer comprising a first side and a second side, the wafer comprising a plurality of die;

a plurality of contact pads coupled to the first side of the wafer;

a metal layer coupled within a recess comprised in the second side of the wafer; and

a mold compound coupled directly to and over the metal layer;

wherein a portion of the wafer is coplanar with a plane formed by a portion of the mold compound facing away from the metal layer;

wherein the metal layer is patterned by a plurality of openings extending through the metal layer;

wherein the mold compound fills the plurality of openings; and

wherein the mold compound comprises a plurality of recesses over each opening of the plurality of openings.

12. The semiconductor wafer of claim 11 , wherein a thickness of the wafer is less than 30 micrometers.

13. The semiconductor wafer of claim 11 , wherein the mold compound covers an entire first surface of the metal layer opposite a second surface of the metal layer facing the second side of the wafer.

14. The semiconductor wafer of claim 11 , further comprising a plurality of bumps coupled over the metal layer.

15. The semiconductor wafer of claim 11 , further comprising a conductive layer coupled between the plurality of contact pads and the wafer.

16. The semiconductor wafer of claim 11 , further comprising a second metal layer coupled over the metal layer.

17. The semiconductor wafer of claim 11 , wherein a thickness of the metal layer is substantially three times a thickness of the wafer.

18. The semiconductor wafer of claim 11 , wherein the plurality of contact pads are exposed through a passivation layer coupled over the wafer.

19. The semiconductor wafer of claim 18 , wherein a surface of the contact pads facing away from the wafer is coplanar with a surface of the passivation layer facing away from the wafer.

20. The semiconductor wafer of claim 11 , further comprising a seed layer directly coupled to the wafer within the recess.