Integrated structure and manufacturing method thereof
A method for fabricating an integrated structure, using a fabrication system having a CMOS line and a photonics line, includes the steps of: in the photonics line, fabricating a first photonics component in a silicon wafer; transferring the wafer from the photonics line to the CMOS line; and in the CMOS line, fabricating a CMOS component in the silicon wafer. Additionally, a monolithic integrated structure includes a silicon wafer with a waveguide and a CMOS component formed therein, wherein the waveguide structure includes a ridge extending away from the upper surface of the silicon wafer. A monolithic integrated structure is also provided which has a photonics component and a CMOS component formed therein, the photonics component including a waveguide having a width of 0.5 μm to 13 μm.
1. An optoelectronic device, comprising:
a first silicon layer having a bottom surface and a top surface; and
a first waveguide in the first silicon layer, the first waveguide having a propagation region confined by:
a base above the bottom surface and below the top surface, and
a first sidewall extending from the base towards the top surface,
wherein each of the base and the first sidewall comprise oxide, and
wherein the first waveguide comprises silicon.
2. The optoelectronic device of claim 1 , further comprising a CMOS component in the first silicon layer.
3. The optoelectronic device of claim 1 , wherein the optoelectronic device is on a silicon-on-insulator wafer comprising:
a silicon substrate;
a buried oxide (BOX) layer above the silicon substrate; and
the first silicon layer above the BOX layer.
4. The optoelectronic device of claim 1 , wherein the optoelectronic device is on a double silicon-on-insulator wafer comprising:
a silicon substrate;
a first buried oxide (BOX) layer above the silicon substrate;
the first silicon layer above the first BOX layer;
a second BOX layer above the first silicon layer; and
a second silicon layer above the second BOX layer.
5. The optoelectronic device of claim 1 , further comprising a second waveguide,
wherein the first and second waveguides overlap each other in a plan view.
6. The optoelectronic device of claim 1 , further comprising a CMOS component in the first silicon layer, wherein a width of the first waveguide is greater than 2 μm and less than or equal to 13 μm.
7. The optoelectronic device of claim 6 , wherein the width of the first waveguide is greater than or equal to 3 μm.
8. The optoelectronic device of claim 7 , wherein the width of the first waveguide is greater than or equal to 4 μm.
9. The optoelectronic device of claim 6 , wherein the optoelectronic device is on a silicon-on-insulator wafer comprising:
a silicon substrate;
a buried oxide (BOX) layer above the silicon substrate; and
the first silicon layer above the BOX layer.
10. The optoelectronic device of claim 9 , further comprising:
an oxide layer on the first silicon layer; and
a conductive trace on the oxide layer and connected to the CMOS component through a via in the oxide layer.
11. The optoelectronic device of claim 6 , wherein the optoelectronic device is on a double silicon-on-insulator (DSOI) wafer comprising:
a silicon substrate;
a first buried oxide (BOX) layer above the silicon substrate;
a second silicon layer above the first BOX layer;
a second BOX layer above the second silicon layer; and
the first silicon layer above the BOX layer.
12. The optoelectronic device of claim 6 , wherein the CMOS component comprises a transistor.
13. The optoelectronic device of claim 6 , wherein the propagation region is further confined by a second sidewall extending from the base towards the top surface, and
wherein the base, the first sidewall, and the second sidewall define a rib of the first waveguide.
14. The optoelectronic device of claim 6 , further comprising a second waveguide,
wherein the first and second waveguides overlap each other in a plan view.
15. The optoelectronic device of claim 6 , further comprising an optically active component or an evanescent active component in the first silicon layer.
16. An optoelectronic device, comprising:
a first silicon layer having a bottom surface and a top surface; and
a first waveguide in the first silicon layer, the first waveguide having a propagation region confined by:
a base above the bottom surface and below the top surface, and
a first sidewall extending from the base towards the top surface,
wherein the propagation region of the first waveguide is further confined by a cap above the base, the first sidewall extending from the base to the cap.
17. An optoelectronic device, comprising:
a first silicon layer having a bottom surface and a top surface; and
a first waveguide in the first silicon layer, the first waveguide having a propagation region confined by:
a base above the bottom surface and below the top surface, and
a first sidewall extending from the base towards the top surface,
wherein the base has an opening exposing the first waveguide to a portion of the first silicon layer below the base.
18. An optoelectronic device, comprising:
a first silicon layer having a bottom surface and a top surface; and
a first waveguide in the first silicon layer, the first waveguide having a propagation region confined by:
a base above the bottom surface and below the top surface, and
a first sidewall extending from the base towards the top surface,
wherein the first waveguide is a rib waveguide comprising a slab region and a rib extending downward from the slab region toward the bottom surface,
wherein the propagation region of the first waveguide is further confined by a second sidewall, and
wherein the rib is defined by the base, the first sidewall, and the second sidewalls.