MOSFET device with undulating channel
A SiC MOSFET device with alternating p-well widths, including an undulating channel, is described. The undulating channel provides current paths of multiple widths, which enables optimization of on-resistance, transconductance, threshold voltage, and channel length. The multi-width p-well region further defines corresponding multi-width Junction FETs (JFETs). The multi-width JFETs enable improved response to a short-circuit event. A high breakdown voltage is obtained by distributing a high electric field in a JFET of a first width into a JFET of a second width.
1. A method of making a SiC semiconductor device, the method comprising:
forming a drift region of a first conductivity type and having a first doping concentration on a substrate;
implanting a channel region in the drift region and along a longitudinal axis, the channel region having alternating well widths with respect to the longitudinal axis, the channel region including a heavily-doped channel region within a lightly-doped channel region of the channel region;
implanting a source region in the channel region, with the heavily-doped channel region between the source region and the lightly-doped channel region; and
forming at least one gate on at least a portion of the source region, at least a portion of the channel region, and on a plurality of junction field effect transistor (JFET) regions disposed between the channel region and the drift region and having a second doping concentration that is greater than the first doping concentration of the drift region, the plurality of JFET regions having alternating JFET widths that alternate in correspondence with the alternating well widths, wherein the lightly-doped channel region is between the heavily-doped channel region and a JFET region of the plurality of JFET regions.
2. The method of claim 1 , wherein implanting the channel region comprises:
providing a mask on the drift region, the mask having an opening corresponding to the alternating well widths of the channel region; and
implanting dopants into the drift region to obtain the lightly-doped region, using the mask.
3. The method of claim 2 , further comprising:
providing a spacer along the opening of the mask to expose a portion of the channel region; and
implanting additional dopants into the portion of the channel region to provide the heavily-doped region.
4. The method of claim 2 , comprising:
providing the mask opening with alternating widths in which adjacent widths differ by at least 0.5 microns.
5. The method of claim 2 , wherein the alternating well widths include a first channel width and a second channel width greater than the first channel width, and further comprising:
implanting body contact regions within the channel region and within the second channel width.
6. The method of claim 1 , wherein the SiC semiconductor device includes at least one Metal Oxide Semiconductor Field Effect Transistor (MOSFET), and further comprising:
forming the substrate on a drain terminal of the MOSFET.
7. The method of claim 1 , further comprising:
implanting body contact regions within the source region and along the longitudinal axis.
8. A method of making a SiC semiconductor device, the method comprising:
forming a drift region of a first conductivity type and a first doping concentration on a substrate of the first conductivity type;
forming a channel region of a second conductivity type within the drift region and disposed along a longitudinal axis, the channel region having a first cross-sectional area orthogonal to the longitudinal axis, in which the channel region has a first width, and a second cross-sectional area orthogonal to the longitudinal axis, in which the channel region has a second width that is smaller than the first width;
forming a source region of the first conductivity type disposed within the channel region;
forming a plurality of junction field effect transistor (JFET) regions between the channel region and the drift region, the plurality of JFET regions being of the first conductivity type and having a second doping concentration that is greater than the first doping concentration of the drift region; and
forming gates disposed along the longitudinal axis and on at least a portion of the source region, the channel region, and the plurality of JFET regions,
wherein the channel region includes a heavily-doped channel region between the source region and a lightly-doped channel region of the channel region, and the lightly-doped channel region is between the heavily-doped channel region and a JFET region of the plurality of JFET regions.
9. The method of claim 8 , wherein forming the plurality of JFET regions comprises:
forming a first JFET region within the first cross-sectional area having a first JFET width; and
forming a second JFET region within the second cross-sectional area having a second JFET width that is wider than the first JFET width.
10. The method of claim 8 , wherein the channel region includes an undulating channel edge along a direction of the longitudinal axis.
11. The method of claim 8 , comprising:
forming a plurality of body contact regions of the second conductivity type within the source region and along the longitudinal axis.
12. The method of claim 8 , wherein a delta between the first width and the second width is at least 0.5 microns.
13. The method of claim 8 , wherein the SiC semiconductor device includes at least one Metal Oxide Semiconductor Field Effect Transistor (MOSFET), and further comprising;
forming a drain terminal of the MOSFET; and
forming the substrate on the drain terminal of the MOSFET.
14. The method of claim 8 , wherein forming the channel region comprises:
providing a mask on the drift region, the mask having an opening corresponding to the first width and the second width of the channel region; and
implanting dopants into the drift region, using the mask.
15. A method of making a SiC semiconductor device, the method comprising:
forming a drift region of a first conductivity type and having a first doping concentration on a substrate of the first conductivity type;
forming a channel region of a second conductivity type within the drift region, the channel region having an undulating channel edge;
forming a source region disposed in the channel region;
forming a plurality of junction field effect transistor (JFET) regions disposed between the channel region and the drift region, the plurality of JFET regions having widths that alternate in correspondence with undulations of the undulating channel edge, the plurality of JFET regions being of the first conductivity type and having a second doping concentration that is greater than the first doping concentration of the drift region;
forming a heavily-doped channel region between the source region and a lightly-doped channel region of the channel region;
forming the lightly-doped channel region between the heavily-doped channel region and a JFET region of the plurality of JFET regions; and
forming at least one gate disposed on at least a portion of the source region, the channel region, and the plurality of JFET regions.
16. The method of claim 15 , wherein forming the channel region comprises:
providing a mask on the drift region, the mask having an opening corresponding to the undulating channel edge; and
implanting dopants into the drift region, using the mask.
17. The method of claim 16 , further comprising:
providing a spacer along the opening of the mask to expose a portion of the channel region; and
implanting additional dopants into the portion of the channel region to provide the heavily-doped channel region.
18. The method of claim 16 , comprising:
providing the mask opening with alternating widths corresponding to the undulating edges, in which adjacent widths differ by at least 0.5 microns.
19. The method of claim 15 , wherein the SiC semiconductor device includes at least one Metal Oxide Semiconductor Field Effect Transistor (MOSFET), and further comprising;
forming a drain terminal of the MOSFET; and
forming the substrate on the drain terminal of the MOSFET.