Array of heat-sinked power semiconductors

1. An array of heat-sinked power semiconductors comprising:

a power semiconductor having a power semiconductor die, a plurality of first terminals and a second terminal, the power semiconductor die having a plurality of semiconductor terminals, each of the first terminals being electrically coupled to an associated one of the semiconductor terminals, the second terminal being a surface mount terminal and electrically coupled to one of the first terminals; and

a heat sink having a heat sink body and a plurality of sets of fins, the heat sink body having a base and a plurality of boundary surfaces, the base being fixedly coupled directly to the surface mount terminal, each of the boundary surfaces terminating at an associated boundary surface plane, each of the boundary surface planes intersecting at least one of the other boundary surface planes, each of the sets of fins being fixedly coupled to the body and extending directly from an associated one of the boundary surfaces;

wherein the sets of fins on an adjacent pair of boundary surfaces are disposed symmetrically about a plane of symmetry that intersects the boundary surface planes of the adjacent pair of boundary surfaces.

2. The array of heat-sinked power semiconductors of claim 1 , wherein a first one of the boundary surfaces intersects at least one of the other boundary surfaces.

3. The array of heat-sinked power semiconductors of claim 1 , wherein the heat sink body has two boundary surfaces.

4. The array of heat-sinked power semiconductors of claim 1 , wherein at least one of the sets of fins is unitarily and integrally formed with the heat sink body.

5. An array of heat-sinked power semiconductors comprising:

a plurality of heat-sinked power semiconductors, each of the heat-sinked power semiconductors having a power semiconductor and a heat sink, the power semiconductor having a power semiconductor die, a plurality of first terminals and a second terminal, the power semiconductor die having a plurality of semiconductor terminals, each of the first terminals being electrically coupled to an associated one of the semiconductor terminals, the second terminal being a surface mount terminal and electrically coupled to one of the first terminals, the heat sink having a heat sink body and a plurality of fins, the heat sink body having a base and an exterior surface, the base being fixedly coupled directly to the surface mount terminal, the exterior surface having a fin mount portion to which the fins extend, at least a portion of the fin mount fin mount portion being non-parallel to base;

wherein the heat-sinked power semiconductors are arranged such that a portion of the fins on one of the heat-sinked power semiconductors and a portion of the fins on an adjacent one of the heat-sinked power semiconductors are disposed in an associated flow channel that is adapted to receive a flow of coolant.

6. The array of heat-sinked power semiconductors of claim 5 , wherein the fin mount portion of each heat sink includes first and second planar segments that are not parallel to one another.

7. The array of heat-sinked power semiconductors claim 6 , wherein the first and second planar segments intersect one another.

8. The array of heat-sinked power semiconductors of claim 5 , wherein the heat sink body and at least a portion of the fins of each heat sink are unitarily and integrally formed.

9. The array of heat-sinked power semiconductors of claim 5 , wherein a first portion of the heat-sinked power semiconductors is arranged in a first row and wherein a second portion of the heat-sinked power semiconductors is arranged in a second row that is parallel to the first row, and wherein the heat-sinked power semiconductors of the first and second portions are nested into one another.

10. The array of heat-sinked power semiconductors of claim 5 , wherein at least a first portion of the heat-sinked power semiconductors is arranged about a central longitudinal axis such that the heat-sinked power semiconductors of the at least the first portion of the heat-sinked power semiconductors are spaced circumferentially about the central longitudinal axis, and wherein a flow channel is formed along the central longitudinal axis.

11. The array of heat-sinked power semiconductors of claim 10 , wherein a second portion of the heat-sinked power semiconductors is arranged about the central longitudinal axis such that the heat-sinked power semiconductors of the second portion of the heat-sinked power semiconductors are spaced circumferentially about the central longitudinal axis, wherein the power semiconductors of the second portion of the heat-sinked power semiconductors are disposed radially outwardly of the power semiconductors of the at least the first portion of the heat-sinked power semiconductors.

12. The array of heat-sinked power semiconductors of claim 11 , wherein the heat sinks of the heat-sinked power semiconductors of the at least the first portion of the heat-sinked power semiconductors and the second portion of the heat-sinked power semiconductors are nested together such that a portion of the fins of one heat-sinked power semiconductor face toward a portion of the fins of an adjacent one of the heat-sinked power semiconductor.

13. The array of heat-sinked power semiconductors of claim 11 , wherein the heat sinks of the heat-sinked power semiconductors of the at least the first portion of the heat-sinked power semiconductors are nested together such that a portion of the fins of one heat-sinked power semiconductor face toward a portion of the fins of an adjacent one of the heat-sinked power semiconductor.