Patent Assignment
Reel/Frame 014268/0115
Assignment of Assignor's Interest
Recorded: 2003-06-23
Received: 2003-06-27
Pages: 28
Assignor
SCHLUMBERGER TECHNOLOGIES, INC.
Executed: 2002-05-10
Assignee
NPTEST, LLC
150 BAYTECH DRIVE, SAN JOSE, CA, 95134, UNITED STATES
Covered Properties
(15)
Method for backside die thinning and polishing of packaged integrated circuits
Application:
10/421,059 →
Open-Loop for Waveform Acquisition
Application:
10/136,710 →
Test System Having Interface Module
Application:
10/132,051 →
Measuring Back-Side Voltage of an Integrated Circuit
Application:
10/123,842 →
Method and Apparatus for Socket Calibration of Integrated Circuit Testers
Application:
10/106,280 →
Test System Algorithmic Program Generators
Application:
10/102,526 →
Test System Formatters Configurable for Multiple Data Rates
Application:
10/101,564 →
Pica System Detector Calibration
Application:
10/079,780 →
Pica System Timing Measurement & Calibration
Application:
10/066,123 →
Comparator Circuit for Differential Swing Comparison and Common-Mode Voltage Comparison
Application:
10/057,134 →
Circuit and Method for Distributing Events in an Event Stream
Application:
10/056,287 →
Photoconductive-Sampling Voltage Measurement
Application:
10/004,018 →
Method for Global Die Thinning and Polishing of Flip-Chip Packaged Integrated Circuits
Application:
09/924,736 →
Chemically Enhanced Focused Ion Beam Micro-Machining of Copper
Application:
09/871,541 →
Through-The-Substrate Investigation of Flip-Chip Ic's
Application:
09/781,488 →