IP Library › Granted Patent US 6,672,947
Granted Patent Utility Small
US 6,672,947 · Confirmation No. 2914

METHOD FOR GLOBAL DIE THINNING AND POLISHING OF FLIP-CHIP PACKAGED INTEGRATED CIRCUITS

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 Code Description Pages PDF
2003-10-27 IFEE Issue Fee Payment (PTO-85B) 3 View
2003-10-27 LET. Miscellaneous Incoming Letter 3 View
2003-10-27 DRW Drawings-only black and white line drawings 6 View
2001-08-07 TRNA Transmittal of New Application 1 View
2001-08-07 SPEC Specification 19 View
2001-08-07 CLM Claims 2 View
2001-08-07 ABST Abstract 1 View
2001-08-07 DRW Drawings-only black and white line drawings 6 View
2001-08-07 OATH Oath or Declaration filed 2 View
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Quick Facts
Patent No.
US 6,672,947
App. No.
09/924,736
Filed
2001-08-07
Granted
2004-01-06
Pub. No.
US20030022603A1
Art Unit
3723
PTA
-46 days