IP Library › Assignment 014428/0584
Patent Assignment
Reel/Frame 014428/0584

Change of Name

Recorded: 2004-03-16 Pages: 8
Assignor
Assignee
HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
20555 SH 249, HOUSTON, TEXAS, 77070
Covered Properties (214)
Multiprocessor Multisystem Communications Network
Patent: 4,667,287 →
Application: 06/437,399 →
Entry Control Store for Enhanced C P U Pipeline Performance
Patent: 4,574,344 →
Application: 06/537,038 →
Ram Based Multiple Breakpoint Logic
Patent: 4,675,646 →
Application: 06/537,039 →
Method of Operating Enhanced Alu Test Hardware
Patent: 4,618,956 →
Application: 06/537,041 →
Multiple Data Patch Cpu Architecture
Patent: 4,800,486 →
Application: 06/537,877 →
Enhanced Cpu Microbranching Architecture
Patent: 4,571,673 →
Application: 06/537,886 →
Multiprocessor Multisystem Communications Network
Patent: 4,663,706 →
Application: 06/542,187 →
Input-Output Multiplexer-Demultiplexer Communications Channel
Patent: 4,667,321 →
Application: 06/551,278 →
Parallel Grounding Scheme
Patent: 4,621,199 →
Application: 06/551,280 →
Fault-Tolerant Communications Controller System
Patent: 4,607,365 →
Application: 06/551,283 →
Communications Method
Patent: 4,646,300 →
Application: 06/551,297 →
Constant Current Drive for Switching Power Supply
Patent: 4,569,011 →
Application: 06/551,299 →
Vector Interrupt System and Method
Patent: 4,628,449 →
Application: 06/551,300 →
Driver Circuit for a Three-State Gate Array Using Low Driving Current
Patent: 4,683,383 →
Application: 06/632,236 →
Structural Support and Thin Panel Assembly
Patent: 4,650,263 →
Application: 06/689,395 →
Electronic Module with Fail-Safe Power Disconnect
Patent: 4,583,803 →
Application: 06/702,185 →
Method and Apparatus for Changing the Master Key in a Cryptographic System
Patent: 4,972,472 →
Application: 06/712,579 →
Self-Checking, Dual Railed, Leading Edge Synchronizer
Patent: 4,700,346 →
Application: 06/733,293 →
Method for Multiprocessor Communications
Patent: 4,718,002 →
Application: 06/741,659 →
Method for Forming Vertical Interconnects in Polyimide Insulating Layers
Patent: 4,661,204 →
Application: 06/791,240 →
Base Drive Circuit for High-Power Switching Transistor
Patent: 4,638,240 →
Application: 06/805,497 →
Circuit Board Barrier Guide
Patent: 4,800,463 →
Application: 06/805,510 →
Instruction Sequencer Branch Mechanism
Patent: 4,837,681 →
Application: 06/839,742 →
Processor Controlled Modifying of Tabled Input/Output Priority
Patent: 4,809,164 →
Application: 06/844,911 →
Method and Apparatus for Clock Management
Patent: 4,746,920 →
Application: 06/845,280 →
Overlapped Control Store
Patent: 4,754,396 →
Application: 06/845,738 →
Multiprocessor Bus Protocol
Patent: 4,888,684 →
Application: 06/845,906 →
Fault Tolerant Modular Subsystems for Computers
Patent: 4,754,397 →
Application: 06/853,537 →
Delay Regulation Circuit
Patent: 5,041,747 →
Application: 06/889,439 →
Pulse Length Indicator
Patent: 4,769,595 →
Application: 06/912,490 →
Emitter Function Logic with Concurrent, Complementary Outputs
Patent: 4,728,818 →
Application: 06/942,669 →
Microcoded Microprocessor with Shared Ram
Patent: 4,825,356 →
Application: 07/031,477 →
System for Performing Group Relative Addressing
Patent: 4,819,165 →
Application: 07/031,486 →
Stack with Unary Encoded Stack Pointer
Patent: 4,899,307 →
Application: 07/036,607 →
Method and Apparatus for Modifying Micro-Instructions Using a Macro- Instruction Pipeline
Patent: 5,005,118 →
Application: 07/036,726 →
Scan Test Apparatus for Digital Systems Having Dynamic Random Access Memory
Patent: 4,827,476 →
Application: 07/039,548 →
Fault Tolerant/Failsafe Current Unit
Patent: 4,761,705 →
Application: 07/039,562 →
Cross-Coupled Checking Circuit
Patent: 4,843,608 →
Application: 07/039,565 →
Electrical Keying for Replaceable Modules
Patent: 4,800,462 →
Application: 07/040,454 →
Diagnostic Apparatus for a Data Processing System
Patent: 4,780,874 →
Application: 07/040,466 →
Input/Output System for Multiprocessors
Patent: 4,821,170 →
Application: 07/040,513 →
Apparatus for Controlling the Connection of an Electrical Module to an Electrical Receptacle
Patent: 4,777,332 →
Application: 07/065,233 →
Queue System with Uninterrupted Transfer of Data Through Intermediate Locations to Selected Queue Location
Patent: 5,179,688 →
Application: 07/068,699 →
System for Measuring Program Execution by Replacing an Executable Instruction with Interrupt Causing Instruction
Patent: 4,910,663 →
Application: 07/072,811 →
Electronic Module Interconnection System
Patent: 4,899,254 →
Application: 07/076,458 →
Ttl-To-Ecl Input Translator/Driver Circuit
Patent: 4,806,800 →
Application: 07/123,507 →
State Machine Checker
Patent: 4,845,712 →
Application: 07/126,525 →
Parity Regeneration Self-Checking
Patent: 4,872,172 →
Application: 07/126,806 →
Data Integrity Checking with Fault Tolerance
Patent: 4,827,478 →
Application: 07/126,812 →
Synchronization Failure Detection
Patent: 4,876,701 →
Application: 07/126,971 →
Two-Stage Synchronizer
Patent: 4,821,295 →
Application: 07/126,997 →
Scan Data Path Coupling
Patent: 4,879,718 →
Application: 07/126,998 →
Version Management Tool
Patent: 4,912,637 →
Application: 07/183,190 →
Scsi Converter
Patent: 4,864,291 →
Application: 07/209,672 →
Electronic Module Interlock and Extraction Mechanism
Patent: 4,885,436 →
Application: 07/238,006 →
A 2:1 Voltage Matrix Encoded I/O Transmission System
Patent: 4,951,050 →
Application: 07/268,422 →
N:1 Time-Voltage Matrix Encoded I/O Transmission System
Patent: 5,034,964 →
Application: 07/268,423 →
Multiple Processor System Having Shared Memory with Private-Write Capability
Patent: 4,965,717 →
Application: 07/283,573 →
Insertion/Extraction Mechanism for Blind Pluggable Modules
Patent: 4,911,647 →
Application: 07/295,333 →
True Ttl to True Ecl Bi-Directional Tristatable Translator Driver Circuit
Patent: 4,931,672 →
Application: 07/318,435 →
Method for Encrypting Transmitted Data Using a Unique Key
Patent: 4,933,971 →
Application: 07/323,485 →
Electric Module Latch Assembly
Patent: 4,931,907 →
Application: 07/331,403 →
Loopback Tester for Testing Field Replaceable Units
Patent: 4,998,069 →
Application: 07/331,467 →
Cell Structure for Linear Array Wafer Scale Integrations with Capability to Open Boundary I/O Bus Without Neighbor Acknowledgement
Patent: 5,203,005 →
Application: 07/346,203 →
One Out of N Checking Apparatus and Method
Patent: 5,067,132 →
Application: 07/353,717 →
Method and Apparatus for Recovering from an Incorrect Branch Prediction in a Processor That Executes a Family of Instructions in Parallel
Patent: 5,072,364 →
Application: 07/356,316 →
Paired Instruction Processor Precise Exception Handling Mechanism
Patent: 5,075,844 →
Application: 07/357,238 →
Apparatus and Method for Reading, Writing, and Refreshing Memory with Direct Virtual or Physical Access
Patent: 5,329,629 →
Application: 07/375,428 →
Deferred Comparison Multiplier Checker
Patent: 5,016,208 →
Application: 07/377,982 →
Multiple Power Supply Sensor for Protecting Shared Processor Buses
Patent: 5,036,455 →
Application: 07/385,330 →
Error Detection for Fiber Distributed Interfaced Optic Link
Patent: 5,068,854 →
Application: 07/406,012 →
System for Protecting a Dc Power Distribution Bus During Hot Servicing
Patent: 5,101,313 →
Application: 07/440,538 →
Apparatus for a Balanced Three Phase Ac Power Supply in a Computer Having Variable Dc Loads
Patent: 5,003,453 →
Application: 07/440,967 →
Falut-Tolerant Computer System with Online Recovery and Reintigration of Redundant Components
Patent: 5,295,258 →
Application: 07/461,250 →
Multi-Board System Having Electronic Keying and Preventing Power to Improperly Connected Plug-in Boards with Improperly Configured Diode Connections
Patent: 5,203,004 →
Application: 07/464,817 →
Self-Calibrating Clock Synchronization System
Patent: 5,036,528 →
Application: 07/471,915 →
Electronic Security Module for Use in Computer Controlled Security Systems
Patent: 341,130 →
Application: 07/514,338 →
Memory System Using Linear Array Wafer Scale Integration Architecture
Patent: 5,287,472 →
Application: 07/570,937 →
Synchronous Processor Unit with Interconnected, Separately Clocked Processor Sections Which Are Automatically Synchronized for Data Transfer Operations
Patent: 5,309,561 →
Application: 07/589,847 →
System for Cache Space Allocation Using Selective Addressing
Patent: 5,132,927 →
Application: 07/594,588 →
Apparatus for Intelligent Reduction of Worst Case Power in Memory Systems
Patent: 5,255,241 →
Application: 07/703,228 →
Method and Apparatus for Mounting, Cooling, Interconnecting, and Providing Power and Data to a Plurality of Electronic Modules
Patent: 5,207,613 →
Application: 07/726,616 →
Method and Apparatus for Executing Tasks by Following a Linked List of Memory Packets
Patent: 5,404,550 →
Application: 07/735,594 →
Breakout Panel Construction
Patent: 5,201,153 →
Application: 07/737,862 →
Electronic Module Switch and Power and Interlock System
Patent: 5,198,627 →
Application: 07/743,003 →
Packaging System
Patent: 5,291,838 →
Application: 07/775,634 →
Method and Apparatus for Providing a Fault Tolerant Network Interface Controller
Patent: 5,774,640 →
Application: 07/781,422 →
System and Method for Ensuring Write Data Integrity in a Redundant Array Data Storage System
Patent: 5,379,417 →
Application: 07/797,470 →
Alignment Mechanism for Blind-Matable Connection for Two or More Connectors
Patent: 5,385,481 →
Application: 07/811,190 →
Redundant Array Parity Caching System
Patent: 5,341,381 →
Application: 07/823,141 →
Environment Monitoring System for Standard Interface Bus Computer Systems
Patent: 5,337,413 →
Application: 07/831,951 →
Fault Tolerant Power Supply for an Array of Storage Devices
Patent: 5,325,363 →
Application: 07/881,434 →
Fail Safe, Fault Tolerant Circuit for Manufacturing Test Logic on Application Specific Integrated Circuits
Patent: 5,404,359 →
Application: 07/906,196 →
Method and System for Implementing Remote Procedure Calls in a Distributed Computer System
Patent: 5,307,490 →
Application: 07/938,102 →
Method and System for Creating Computer-Program-Based Applications with Developer Specified Look and Feel
Patent: 5,818,445 →
Application: 07/943,221 →
Injector/Ejector Latch Lock Mechanism
Patent: 5,321,962 →
Application: 08/006,188 →
Fault-Tolerant Computer System with Hidden Local Memory Refresh
Patent: 5,473,770 →
Application: 08/025,229 →
Electronic Assembly with Improved Grounding and Emi Shielding
Patent: 5,311,408 →
Application: 08/055,405 →
Filtered Connector/Adaptor for Unshielded Twisted Pair Wiring
Patent: 5,346,410 →
Application: 08/076,028 →
System and Method for Performing Improved Pseudo-Random Testing of Systems Having Multi Driver Buses
Patent: 5,951,703 →
Application: 08/083,419 →
Scannable Interface to Nonscannable Microprocessor
Patent: 5,428,623 →
Application: 08/086,341 →
Power on System
Patent: 5,834,958 →
Application: 08/086,955 →
Chip Clock Skew Control Method and Apparatus
Patent: 5,467,033 →
Application: 08/087,226 →
Power Regulation for Redundant Battery Supplies
Patent: 5,430,365 →
Application: 08/087,241 →
Programmable Error-Checking Matrix for Digital Communication System
Patent: 5,396,505 →
Application: 08/087,545 →
Multiple Frequency Output Clock Generator System
Patent: 5,371,417 →
Application: 08/087,556 →
Method of State Determination in Lock-Stepped Processors
Patent: 5,435,001 →
Application: 08/088,562 →
High Speed Processor Bus Extension
Patent: 5,371,863 →
Application: 08/125,620 →
Method and Apparatus for Fault Tolerant Connection of a Computing System to Local Area Networks
Patent: 5,448,723 →
Application: 08/137,436 →
Method for Sorting and Storing Data Employing Dynamic Sort Tree Reconfiguration in Volatile Memory
Patent: 5,619,693 →
Application: 08/236,513 →
Apparatus for Cooling a Plurality of Electrical Components Mounted on a Printed Circuit Board
Patent: 5,615,086 →
Application: 08/245,296 →
Boundary Scan System with Improved Error Reporting
Patent: 5,513,189 →
Application: 08/248,801 →
Flexible Bus Routing Structure
Patent: 5,536,176 →
Application: 08/248,805 →
Method and Apparatus for Fault-Tolerant Multiprocessing System Recovery from Power Failure or Drop-Outs
Patent: 5,928,368 →
Application: 08/265,585 →
Real Time Observation Serial Scan Test Architecture
Patent: 6,035,262 →
Application: 08/266,431 →
Interconnect Testing Using Non-Compatible Scan Architectures
Patent: 6,029,263 →
Application: 08/268,370 →
Redundant Power Mixing Element with Fault Detection for Dc-to-Dc Converter
Patent: 5,488,531 →
Application: 08/268,918 →
Control Interface for Customer Replaceable Fan Unit
Patent: 5,436,827 →
Application: 08/269,187 →
System for Multiplexing Prioritized Virtual Channels Onto Physical Channels Where Higher Priority Virtual Will Pre-Empt a Lower Priority Virtual or a Lower Priority Will Wait
Patent: 5,619,647 →
Application: 08/316,402 →
Method and Apparatus for Translating Source Code from One High-Level Computer Language to Another
Patent: 5,768,564 →
Application: 08/319,682 →
Method and Apparatus for Testing and Analyzing the Conformance of a Proposed Set of Requirements for a Proposed Network Management Application
Patent: 5,812,436 →
Application: 08/326,771 →
Method and Apparatus for Preparing a Suite of Test Scripts for Testing a Proposed Network Management Application
Patent: 5,715,373 →
Application: 08/326,778 →
Module Dependency Based Incremental Compiler and Method
Patent: 5,586,328 →
Application: 08/328,171 →
Decentralized Bus Arbitration System Which Continues to Assert Bus Request Signal to Preclude Other from Asserting Bus Request Signal Unit Information Transfer on the Bus Has Been Completed
Patent: 5,546,587 →
Application: 08/332,617 →
Method and Apparatus for Translating Source Code from One High-Level Computer Language to Another
Patent: 5,842,204 →
Application: 08/332,966 →
Method and Apparatus for Analyzing Test Results Obtained by Applying a Binary Table and a Suite of Test Scripts to a Test Subsystem Control Facility for a Distributed Systems Network
Patent: 5,724,273 →
Application: 08/350,230 →
Hash-Based Database Grouping System and Method
Patent: 5,511,190 →
Application: 08/376,026 →
Multi-Volume Audit Trails for Fault Tolerant Computers
Patent: 5,590,274 →
Application: 08/377,075 →
Protocol Timer and Method of Using Same
Patent: 5,577,237 →
Application: 08/377,301 →
A Method for Providing Recovery Froma Failure in a System Utilizing Distributed Audit
Patent: 5,832,203 →
Application: 08/377,381 →
Method and Apparatus for Preventing Inadvertent Changes to System-Critical Files in a Computing System
Patent: 5,978,914 →
Application: 08/377,385 →
Ordered and Reliable Maintenance of Inter-Process Relationships in a Distributed Multiprocessor
Patent: 5,577,261 →
Application: 08/377,386 →
Ordered and Reliable Signal Delivery in a Distributed Multiprocessor
Patent: 5,630,140 →
Application: 08/377,387 →
A Transaction Monitor Process with Prearranged Modules for a Multiprocessor System
Patent: 5,576,945 →
Application: 08/377,573 →
Remote Duplicate Database Facility with Database Replication Support for Online Ddl Operations
Patent: 5,745,753 →
Application: 08/377,881 →
Latency Reduction and Routing Arbitration for Network Message Routers
Patent: 5,694,121 →
Application: 08/469,756 →
Method and Apparatus for Context Sensitive Pathsend
Patent: 5,889,957 →
Application: 08/472,227 →
Apparatus and Method for Scan-Based Testing in an Object-Oriented Programming Environment
Patent: 5,606,661 →
Application: 08/472,306 →
Method of Synchronizing a Pair of Central Processor Units for Duplex, Lock-Step Operation by Copying Data into a Corresponding Locations of Another Memory
Patent: 5,751,955 →
Application: 08/473,541 →
Method for Verifying Responses to Messages Using a Barrier Message
Patent: 5,675,579 →
Application: 08/474,770 →
Network Message Routing Using Routing Table Information and Supplemental Enable Information for Deadlock Prevention
Patent: 5,914,953 →
Application: 08/474,772 →
System and Method for Providing a Fault Tolerant Computer Program Runtime Support Environment
Patent: 5,621,885 →
Application: 08/475,195 →
A Encoding for Communicating Data and Commands
Patent: 5,867,501 →
Application: 08/477,807 →
Plurality of Services Having Identical Customer Information Control Procedure Functions Using Temporary Storage File of a Predetermined Server for Centrally Storing Temporary Data Records
Patent: 5,682,507 →
Application: 08/478,057 →
Customer Information Control System and Method in a Loosely Coupled Parallel Processing Environment
Patent: 5,687,372 →
Application: 08/478,058 →
Customer Information Control System and Method with Transaction Serialization Control Functions in a Loosely Coupled Parallel Processing Environment
Patent: 5,790,868 →
Application: 08/479,701 →
Customer Information Control System and Method with Api Start and Cancel Transaction Functions in a Loosely Coupled Parallel Processing Environment
Patent: 5,630,133 →
Application: 08/479,702 →
Method and Apparatus for a Complete Sql Subquery Elimination Process
Patent: 5,724,570 →
Application: 08/480,963 →
Database Management System with Improved Indexed Accessing
Patent: 5,778,354 →
Application: 08/481,649 →
Interrupt Message Delivery Identified by Storage Location of Received Interrupt Data
Patent: 5,675,807 →
Application: 08/481,749 →
Storage Access Validation to Data Messages Using Partial Storage Address Data Indexed Entries Containing Permissible Address Range Validation for Message Source
Patent: 5,964,835 →
Application: 08/482,618 →
Synchronized Data Transmission Between Elements of a Processing System
Patent: 5,574,849 →
Application: 08/482,628 →
Routing Arbitration for Shared Resources
Patent: 5,710,549 →
Application: 08/483,663 →
Clock Circuits for Synchronized Processor Systems Having Clock Generator Circuit with a Voltage Control Oscillator Producing a Clock Signal Synchronous with a Master Clock Signal
Patent: 5,689,689 →
Application: 08/483,748 →
A Logical, Fail-Functional, Dual Central Processor Units Formed from Three Processor Units
Patent: 5,838,894 →
Application: 08/484,281 →
Apparatus for Detecting Divergence Between a Pair of Duplexed, Synchronized Processor Elements
Patent: 5,790,776 →
Application: 08/485,053 →
Fail-Fast, Fail-Functional, Fault-Tolerant Multiprocessor System
Patent: 5,751,932 →
Application: 08/485,217 →
Method to Improve Tolerance of Non-Homogeneous Power Outages
Patent: 5,687,308 →
Application: 08/487,941 →
Direct Bulk Data Transfers
Patent: 5,805,920 →
Application: 08/556,618 →
Expandable Modular Computer System
Patent: 5,602,721 →
Application: 08/572,903 →
Computer System Data I/O by Reference Among Multiple Cpus
Patent: 5,931,903 →
Application: 08/575,533 →
Module Latch Assembly
Patent: 5,725,324 →
Application: 08/576,747 →
Module Connection Mechanism
Patent: 5,785,397 →
Application: 08/576,750 →
Computer System Data I/O by Reference Among I/O Devices and Multiple Memory Units
Patent: 5,954,794 →
Application: 08/578,366 →
System for Transferring a Data Stream to a Requestor Without Copying Data Segments to Each One of Multiple Data Source/Sinks During Data Stream Building
Patent: 5,941,959 →
Application: 08/578,409 →
System for Transferring Data Over a Network in Which a Data Source Sends Only a Descriptor Which a Data Sink Uses to Retrieve Data
Patent: 5,852,719 →
Application: 08/578,410 →
Computer System Data I/O by Reference Among Cpus and I/O Devices
Patent: 5,790,807 →
Application: 08/578,411 →
Spoon-Feed Initialization in a Multiprocessor System
Patent: 5,682,528 →
Application: 08/578,889 →
Flexible Implementation of Distributed Dc Power
Patent: 5,861,684 →
Application: 08/579,376 →
Method and Apparatus for Dynamically Presenting Graphical Representation of Instrumentation
Patent: 5,889,530 →
Application: 08/616,028 →
End-To-End Session Recovery
Patent: 5,754,752 →
Application: 08/625,532 →
Clock Error Detection Circuit
Patent: 5,930,275 →
Application: 08/659,768 →
System for Maintaining Polarity Synchronization During Ami Data Transfer
Patent: 5,742,135 →
Application: 08/693,000 →
Connector Bracket for Printed Wiring Board
Patent: 5,833,494 →
Application: 08/693,822 →
Method for Keeping Accurate Time in a Computer System
Patent: 5,826,066 →
Application: 08/694,073 →
An Improved System and Method for Optimizing Database Queries
Patent: 5,822,747 →
Application: 08/702,106 →
Interprocessor Messaging System
Patent: 5,915,088 →
Application: 08/761,116 →
Remote Duplicate Database Facility with Improved Throughput and Fault Tolerance and Featuring Subset Audit Record Marking and Storage
Patent: 5,835,915 →
Application: 08/761,725 →
System and Method for Optimizing Database Queries with Improved Performance Enhancements
Patent: 6,021,405 →
Application: 08/763,407 →
Method and Apparatus for Configuring Routing Paths of a Network Communicatively Interconnecting a Number of Processing Elements
Patent: 5,983,269 →
Application: 08/764,115 →
Remote Duplicate Database Facility Featuring Safe Master Audit Trail (Safemat) Checkpointing
Patent: 5,794,252 →
Application: 08/767,452 →
System and Method for Database Query Optimization
Patent: 5,819,255 →
Application: 08/773,695 →
Method and Apparatus for Providing Fraud Protection Mediation in a Mobile Telephone System
Patent: 6,085,083 →
Application: 08/781,264 →
Method and Apparatus for Distributed Agreement on Processor Membership in a Multi-Processor System
Patent: 5,884,018 →
Application: 08/789,257 →
Method and Apparatus for Node Pruning a Multi-Processor System for Maximal, Full Connection During Recovery
Patent: 6,002,851 →
Application: 08/790,030 →
Method an Apparatus for Tolerance of Lost Timer Ticks During Recovery of a Multi-Processor System
Patent: 5,892,895 →
Application: 08/790,268 →
Method and Apparatus for Split-Brain Avoidance in a Multi-Processor System
Patent: 5,991,518 →
Application: 08/790,269 →
System and Method for Stopping Updates at a Specified Timestamp in a Remote Duplicate Database Facility
Patent: 5,799,322 →
Application: 08/790,542 →
Remote Duplicate Databased Facility with Triple Contingency Protection
Patent: 5,799,323 →
Application: 08/790,544 →
Blind Alignment Method and Apparatus for Circuit Boards
Patent: 5,872,701 →
Application: 08/807,608 →
Method and System for Providing Interpretive Access to an Object System
Patent: 5,983,019 →
Application: 08/819,535 →
Method and Apparatus for Checking Transactions in a Computer System
Patent: 5,875,291 →
Application: 08/840,138 →
Method and System for Providing Fault Tolerant Access Between Clients and a Server
Patent: 5,948,108 →
Application: 08/873,446 →
Method for Input and Output of Structures for the Java Language
Patent: 6,298,389 →
Application: 08/879,737 →
System and Method for Sychronizing a Large Database and Its Replica
Patent: 5,884,328 →
Application: 08/920,401 →
Method for Sequential and Consistent Startup and/or Reload of Multiple Processor Nodes in a Multiple Node Cluster
Patent: 5,964,838 →
Application: 08/940,348 →
Method of Comparing Replicated Databases Using Checksum Information
Patent: 5,974,574 →
Application: 08/940,447 →
A Fault Tolerant Method of Maintaining and Distributing Configuration Information in a Distributed Processing System
Patent: 6,092,213 →
Application: 08/941,478 →
Method and Apparatus for Detecting Failed Batteries
Patent: 6,020,743 →
Application: 08/955,433 →
Method and Apparatus Determining and Using Hash Functions and Hash Values
Patent: 6,226,629 →
Application: 09/034,216 →
Computer Architecture Capable of Concurrent Issuance and Execution of General Purpose Multiple Instructions
Patent: 6,009,506 →
Application: 09/059,271 →
Method for Multilevel Data Integrity in a Computer Node Cluster Environment
Patent: 6,122,629 →
Application: 09/070,897 →
Root Filesystem Failover in a Single System Image Environment
Patent: 6,249,879 →
Application: 09/071,048 →
Filesystem Failover in a Single System Image Environment
Patent: 6,247,139 →
Application: 09/071,145 →
Method and Apparatus for Sharing Objects and Object State Between Processes
Patent: 6,301,557 →
Application: 09/132,945 →
Method and Apparatus for Managing Invalidation of Virtual Memory Mapping Table Entries
Patent: 6,279,094 →
Application: 09/137,763 →
Interval -Timing Facility Using Overbuilt Hierarchical Timing Wheels
Patent: 6,115,826 →
Application: 09/153,056 →
Efficient Inter-Task Queue Protocol
Patent: 6,341,302 →
Application: 09/160,367 →
Histogram Synthesis Modeler for a Database Query Optimizer
Patent: 6,263,345 →
Application: 09/162,245 →
Method and Apparatus for Record Addressing in Partitioned Files
Patent: 6,473,774 →
Application: 09/162,256 →
Method and Apparatus for Omnibus Wiring of Virtual Mapping Table Entries
Patent: 6,279,095 →
Application: 09/189,601 →
Customer Information Control System Application Programming Interface with Transient Data Functions, in a Loosely Coupled Data Processing Environment
Patent: 6,442,568 →
Application: 09/210,512 →
System and Method for Multiplication Modulo (2N + 1)
Patent: 6,321,247 →
Application: 09/222,254 →
Portable Device for Communicating with Magnetic Stripe and Integrated Circuit Cards
Patent: 408,377 →
Application: 29/086,854 →
Related Assignments (2)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest Mar 16, 2004
From: COMPAQ COMPUTER CORPORATION
To: COMPAQ INFORMATION TECHNOLOGIES GROUP, L.P., A TEXAS LIMITED PARTNERSHIP
Reel/Frame 014506/0133 →
Merger Mar 16, 2004
From: TANDEM COMPUTERS INCORPORATED
To: COMPAQ COMPUTER CORPORATION, A DELAWARE CORPORATION
Reel/Frame 014506/0598 →