Patent Assignment
Reel/Frame 014788/0733
Assignment of Assignor's Interest
Recorded: 2003-12-12
Pages: 6
Assignor
SEIKO EPSON CORPORATION
Executed: 2001-05-24
Assignee
TRANSMETA CORPORATION
3940 FREEDOM CIRCLE, SANTA CLARA, CALIFORNIA, 95054
Covered Properties
(18)
Risc Microprocessor Architecture Implementing Multiple Typed Register Sets
Patent:
5,493,687 →
Application:
07/726,773 →
A System and Method for Extraction, Alignment and Decoding of Cisc Instructions into a Nano-Instruction Bucket for Execution by a Risc Computer
Patent:
5,438,668 →
Application:
07/857,599 →
Superscalar Risc Instruction Scheduling
Patent:
5,497,499 →
Application:
08/219,425 →
Method for Translating Non-Native Instructions to Native Instructions and Combining Them into a Final Bucket for Processing on a Host Processor
Patent:
5,546,552 →
Application:
08/440,225 →
System for Translating Non-Native Instructions to Native Instructions and Combining Them into a Final Bucket for Processing on a Host Processor
Patent:
5,619,666 →
Application:
08/460,272 →
Risc Microprocessor Architecture Implementing Multiple Typed Register Sets
Patent:
5,560,035 →
Application:
08/465,239 →
Superscalar Risc Instruction Scheduling
Patent:
5,737,624 →
Application:
08/594,401 →
Risc Microprocessor Architecture Implementing Multiple Typed Register Sets
Patent:
5,682,546 →
Application:
08/665,845 →
Superscalar Microprocessor for Out-of-Order and Concurrently Executing at Least Two Risc Instructions Translating from in-Order Cisc Instructions
Patent:
5,983,334 →
Application:
08/784,339 →
Risc Microprocessor Architecture Implementing Multiple Typed Register Sets
Patent:
5,838,986 →
Application:
08/937,361 →
Superscalar Risc Instruction Scheduling
Patent:
5,974,526 →
Application:
08/990,414 →
Risc Microprocessor Architecture Implementing Multiple Typed Register Sets
Patent:
6,044,449 →
Application:
09/188,708 →
Superscalar Risc Instruction Scheduling
Patent:
6,289,433 →
Application:
09/329,354 →
System and Method for Translating Non-Native Instruction to Native Instructions for Processing on a Host Processor
Patent:
6,263,423 →
Application:
09/401,860 →
RISC microprocessor architecture implementing multiple typed register sets
Patent:
6,249,856 →
Application:
09/480,136 →
Risc Microprocessor Architecture Implementing Multiple Typed Register Sets
System and Method for Translating Non-Native Instructions to Native Instructions for Processing on a Host Processor
Superscalar Risc Instruction Scheduling
Related Assignments
(17)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Dec 12, 2003
From: COON, BRETT; MIYAYAMA, YOSHIYUKI; NGUYEN, LE TRONG; WANG, JOHANNES
To: S-MOS SYSTEMS, INC.
Reel/Frame 014788/0468 →
Assignment of Assignor's Interest
Dec 12, 2003
From: S-MOS SYSTEMS, INC.
To: SEIKO EPSON CORPORATION
Reel/Frame 014788/0454 →
Assignment of Assignor's Interest
Dec 12, 2003
From: GARG, SANJIV; LENTZ, DEREK J.; NGUYEN, LE TRONG; CHEN, CHO-LONG
To: S-MOS SYSTEMS, INC.
Reel/Frame 014788/0462 →
Assignment of Assignor's Interest
Dec 12, 2003
From: S-MOS SYSTEMS, INC.
To: SEIKO EPSON CORPORATION
Reel/Frame 014788/0458 →
Assignment of Assignor's Interest
Dec 12, 2003
From: S-MOS SYSTEMS, INC.
To: SEIKO EPSON CORPORATION
Reel/Frame 014788/0444 →
Assignment of Assignor's Interest
Dec 12, 2003
From: GARG, SANJIV; IADONATO, KEVIN RAY; NGUYEN, LE TRONG; WANG, JOHANNES
To: S-MOS SYSTEMS, INC.
Reel/Frame 014788/0452 →
Assignment of Assignor's Interest
Dec 17, 2003
From: GARG, SANJIV; LENTZ, DEREK J.; NGUYEN, LE TRONG; CHEN, SHO-LONG
To: S-MOS SYSTEMS, INC.
Reel/Frame 014201/0448 →
Assignment of Assignor's Interest
Dec 17, 2003
From: COON, BRETT; MIYAYAMA, YOSHIYUKI; NGUYEN, LE TRONG; WANG, JOHANNES
To: S-MOS SYSTEMS, INC.
Reel/Frame 014201/0416 →
Assignment of Assignor's Interest
Dec 17, 2003
From: GARG, SANJIV; IADONATO, KEVIN RAY; NGUYEN, LE TRONG; WANG, JOHANNES
To: S-MOS SYSTEMS, INC.
Reel/Frame 014201/0400 →
Assignment of Assignor's Interest
Dec 17, 2003
From: S-MOS SYSTEMS INC.
To: SEIKO EPSON CORPORATION
Reel/Frame 014201/0402 →
Assignment of Assignor's Interest
Dec 17, 2003
From: S-MOS SYSTEMS, INC.
To: SEIKO EPSON CORPORATION
Reel/Frame 014201/0406 →
Assignment of Assignor's Interest
Dec 17, 2003
From: SEIKO EPSON CORPORATION
To: TRANSMETA CORPORATION
Reel/Frame 014201/0410 →
Assignment of Assignor's Interest
Dec 17, 2003
From: S-MOS SYSTEMS, INC.
To: SEIKO EPSON CORPORATION
Reel/Frame 014201/0429 →
Assignment of Assignor's Interest
Mar 4, 2009
From: TRANSMETA LLC
To: INTELLECTUAL VENTURE FUNDING LLC
Reel/Frame 022343/0219 →
Merger
Apr 3, 2009
From: TRANSMETA CORPORATION
To: TRANSMETA LLC
Reel/Frame 022494/0500 →
Assignment of Assignor's Interest
Jan 4, 2020
From: INTELLECTUAL VENTURES ASSETS 158 LLC
To: HANGER SOLUTIONS, LLC
Reel/Frame 051486/0425 →
Assignment of Assignor's Interest
Feb 1, 2020
From: INTELLECTUAL VENTURES HOLDING 81 LLC
To: INTELLECTUAL VENTURES ASSETS 158 LLC
Reel/Frame 051777/0017 →