Patent Assignment
Reel/Frame 016027/0773
Assignment of Assignor's Interest
Recorded: 2004-11-29
Pages: 3
Assignors
ICHIGE, MASAYUKI
Executed: 2004-08-25
ARAI, FUMITAKA
Executed: 2004-08-25
SUGIMAE, KIKUKO
Executed: 2004-08-25
Assignee
KABUSHIKI KAISHA TOSHIBA
1-1, SHIBAURA 1-CHOME, MINATO-KU, TOKYO, JAPAN
Covered Property
(1)
Nonvolatile Semiconductor Memory Cell Matrix with Divided Write/Erase, a Method for Operating the Same, Monolithic Integrated Circuits and Systems