Nonvolatile semiconductor memory cell matrix with divided write/erase, a method for operating the same, monolithic integrated circuits and systems
A nonvolatile semiconductor memory includes a plurality of word lines WL; a plurality of bit lines BL; memory cell transistors having a charge storage layer arranged in the column whose charge storage state is controlled by one of the word lines; memory cell transistor rows MSGm, MSGn functioning as select gate lines by injecting a charge into the charge storage layer of a memory cell transistor to form an enhancement mode transistor. Any one of a first select gate transistor or a second transistor, or both may be formed by a memory cell transistor functioning as a select gate transistor.
1. A nonvolatile semiconductor memory device, comprising:
a semiconductor substrate including a first memory cell region, a second memory cell region located adjacent to the first memory cell region in a first direction, and an active area extending in the first direction and continuously arranged in the first and second memory cell regions;
a first select gate line located in the first memory cell region and extending in a second direction perpendicular to the first direction;
a first select gate transistor located between the first select gate line and the active area in the first memory cell region;
a second select gate line located in the first memory cell region and arranged in parallel with the first select gate line;
a second select gate transistor located between the second select gate line and the active area in the first memory cell region;
a plurality of first word lines located between the first and second gate lines in the first memory cell region, each first word line arranged in parallel with the first select gate line;
a plurality of first memory cell transistors located between the first word lines and the active area in the first memory cell region;
a third select gate line located in the second memory cell region and extending in the second direction;
a third select gate transistor located between the third select gate line and the active area in the second memory cell region;
a fourth select gate line located in the second memory cell region and arranged in parallel with the third select gate line;
a fourth select gate transistor located between the fourth select gate line the active area in the second memory cell region;
a plurality of second word lines located between the third and fourth select gate lines in the second memory cell region, each second word line arranged in parallel with the third select gate line;
a plurality of second memory cell transistors located between the second word lines and the active area in the second memory cell region; and
a controller located adjacent to the second memory cell region in the second direction, the controller connected to the second word lines and arbitrarily setting one of the second memory cell transistors as an additional select gate transistor through a corresponding one of the second word lines,
wherein the number of second memory cell transistors between the third select gate transistor and the additional select gate transistor in the second memory cell region is less than the number of first memory cell transistors between the first and second select gate transistors, a first data to be accessed at a first access speed is stored in the first memory cell transistors in the first memory cell region and a second data to be accessed in second access speed, which is faster than the first access speed, is stored in the second memory cell transistors located between the third and additional select gate transistors in the second memory cell region.
2. The nonvolatile semiconductor memory device of claim 1 , wherein the first and second select gate transistors include a first gate length that is same as a second gate length of the first memory cell transistors.
3. The nonvolatile semiconductor memory device of claim 1 , wherein the controller includes a row decoder circuit supplying a writing voltage to the first and second word lines.
4. The nonvolatile semiconductor memory device of claim 1 , wherein the first and second memory cell transistors include a charge storage layer having a floating gate electrode, respectively.
5. The nonvolatile semiconductor memory device of claim 1 , wherein the first and second memory cell transistors include a charge storage layer having a silicon nitride film, respectively.
6. The nonvolatile semiconductor memory device of claim 1 , wherein the second data is a program address data.
7. The nonvolatile semiconductor memory device of claim 1 , wherein the second data is an encryption code data.