Patent Assignment
Reel/Frame 017166/0087
Assignment of Assignor's Interest
Recorded: 2005-10-31
Pages: 3
Assignors
SADAKANE, TOSHIYUKI
Executed: 2005-03-30
SAITO, KEN
Executed: 2005-03-30
INOUE, YOSHIO
Executed: 2005-03-30
Assignee
RENESAS TECHNOLOGY CORP.
4-1, MARUNOUCHI 2-CHOME, CHIYODA-KU, TOKYO, JAPAN
Covered Property
(1)
Routing Analysis Method, Logic Synthesis Method and Circuit Partitioning Method for Integrated Circuit
Related Assignments
(4)
Other recorded transfers of the patent in this record — the chain of ownership.
Assignment of Assignor's Interest
Apr 22, 2005
From: SADAKANE, YOSHIYUKI; SAITO, KEN; INOUE, YOSHIO
To: RENESAS TECHNOLOGY CORP.
Reel/Frame 016498/0084 →
Merger
Aug 27, 2010
From: RENESAS TECHNOLOGY CORPORATION
To: NEC ELECTRONICS CORPORATION
Reel/Frame 024892/0877 →
Change of Name
Aug 27, 2010
From: NEC ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 024944/0437 →
Change of Address
Nov 29, 2017
From: RENESAS ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 044928/0001 →