Routing analysis method, logic synthesis method and circuit partitioning method for integrated circuit
The present invention relates to a routing analysis method for performing a routing analysis on an integrated circuit from a netlist which is information on a plurality of cells constituting the integrated circuit and routes connecting the cells, and the routing analysis method comprises a step (Step 1 ) of obtaining the sum of areas of a plurality of cells, the number of cells or the number of routes connecting the cells from the netlist, to be defined as a constant C, and calculating a layout area S which is an area of a square layout region, by dividing the constant C by a predetermined constant U, a step (Step 2 ) of calculating a total route length L by multiplying a half perimeter length H of the layout region having the layout area S obtained in Step 1 by a predetermined coefficient α, and a step (Step 3 ) of calculating a routing difficulty index by dividing the total route length L by the layout area S. Thus, the present invention provides a routing analysis method for an integrated circuit, which, allows calculation of routing difficulty index with high accuracy of prediction.
1. A routing analysis method for performing a routing analysis on an integrated circuit from a netlist, which is information on a plurality of cells constituting said integrated circuit and routes connecting said plurality of cells, comprising the steps of:
(a) obtaining a sum of areas of said plurality of cells, a number of said plurality of cells or a number of said routes connecting said plurality of cells from said netlist, to be defined as a first constant, and calculating a layout area which is an area of a layout region, by dividing said first constant by a predetermined second constant;
(b) calculating a total route length by multiplying a predetermined perimeter length of said layout region having said layout area obtained in said step (a) by a predetermined coefficient; and
(c) calculating a routing difficulty index by dividing said total route length by said layout area.
2. The routing analysis method for an integrated circuit according to claim 1 , wherein
said predetermined coefficient is obtained by dividing said total route length, which is measured by roughly arranging said plurality of cells in said layout region having a predetermined half perimeter length, by said predetermined half perimeter length.
3. The routing analysis method for an integrated circuit according to claim 1 , wherein
said predetermined second constant is a numerical value indicating a ratio of an area of cells which are allowed to be arranged in said layout region to a unit area.
4. A routing analysis method for performing a routing analysis on an integrated circuit from a netlist, which is information on a plurality of cells constituting said integrated circuit and routes connecting said plurality of cells, comprising the steps of:
(a) obtaining a sum of areas of said plurality of cells, a number of said plurality of cells or a number of said routes connecting said plurality of cells from said netlist, to be defined as a first constant, and calculating a layout area which is an area of a layout region, by dividing said first constant by a predetermined second constant;
(b) calculating a route length of each net by multiplying a half perimeter length of said layout region by a predetermined coefficient of said each net and then obtaining a total route length by integrating said route length of said each net; and
(c) calculating a routing difficulty index by dividing said total route length by said layout area.
5. The routing analysis method for an integrated circuit according to claim 4 , wherein
said predetermined coefficient is obtained by dividing said route length of said net, which is measured by roughly arranging said plurality of cells in said layout region having a predetermined half perimeter length, by said predetermined half perimeter length.
6. The routing analysis method for an integrated circuit according to claim 4 , wherein
said predetermined second constant is a numerical value indicating a ratio of an area of cells which are allowed to be arranged in said layout region to a unit area.