Patent Assignment
Reel/Frame 018503/0905
Assignment of Assignor's Interest
Recorded: 2006-11-02
Pages: 3
Assignor
YODA, KENICHI
Executed: 2006-10-10
Assignee
NEC ELECTRONICS CORPORATION
1753 SHIMONUMABE, NAKAHARA-KU, KAWASAKI, KANAGAWA, 211-8668, JAPAN
Covered Property
(1)
Layout Design Method of Semiconductor Integrated Circuit Having Well Supplied with Potential Different from Substrate Potential.
Related Assignments
(2)
Other recorded transfers of the patent in this record — the chain of ownership.