Layout design method of semiconductor integrated circuit having well supplied with potential different from substrate potential
View Patent ↗Design time (TAT) is reduced in a layout design of a semiconductor integrated circuit having a well supplied with a potential different from a substrate potential. A layout design method of the present invention includes preparing a first cell pattern placed on a semiconductor substrate of a first conductive type, preparing a second cell pattern having a deep well of a second conductive type, placing the first cell pattern in a first circuit region, and placing the second cell pattern in a second region different from the first circuit region. This reduces TAT in chip design.
1. A method of placing a cell of a semiconductor integrated circuit comprising:
placing a first cell pattern, which has both first n-type and p-type transistors, on a semiconductor substrate;
placing a second cell pattern, which has both second n-type and p-type transistors and a deep well below the second n-type and p-type transistors, on the semiconductor substrate;
placing the first cell pattern in a substrate potential region of the semiconductor substrate;
placing the second cell pattern in a plurality of separating well regions of the semiconductor substrate;
placing a third cell pattern, having a cell layout including a well wall that reaches the deep well from a surface of the semiconductor substrate, around the plurality of separating well regions of the semiconductor substrate; and
providing a space between at least one of the plurality of separating well regions and the substrate potential region or at least one of the plurality of separating well regions and another of the plurality of separating well regions based on the cell layout of the third cell pattern.
2. The method of placing a cell of a semiconductor integrated circuit according to claim 1 , wherein the space between the at least one of the plurality of separating well regions and the substrate potential region or the at least one of the plurality of separating well regions and the another of the plurality of separating well regions is determined according to a design standard.
3. The method of placing a cell of a semiconductor integrated circuit according to claim 1 , wherein the separating well regions have a potential different from the potential of the substrate potential region.
4. The method of placing a cell of a semiconductor integrated circuit according to claim 1 , wherein the first and second cell patterns are placed on the semiconductor substrate through a design process that is performed on a computer.