IP Library Assignment 019022/0494
Patent Assignment
Reel/Frame 019022/0494

Assignment of Assignor's Interest

Recorded: 2007-03-07 Pages: 2
Assignor
HITACHI, LTD.
Executed: 2003-09-12
Assignee
RENESAS TECHNOLOGY CORPORATION
4-1, MARUNOUCHI 2-CHOME, CHIYODA-KU, TOKYO, JAPAN
Covered Property (1)
Method of Fabricating a Semiconductor Integrated Circuit That Includes Patterning a Semiconductor Substrate with a First Photomask That Uses Metal for Blocking Light and Patterning the Same Substrate with a Second Photomask That Uses Organic Resin for Blocking Ligh
Patent: 7,361,530 →
Application: 11/714,837 →
Publication: US 2007/0155052
Related Assignments (3)
Other recorded transfers of the patent in this record — the chain of ownership.
Assignment of Assignor's Interest Mar 7, 2007
From: TERASAWA, TSUNEO; TANAKA, TOSHIHIKO; MIYAZAKI, KO; HASEGAWA, NORIO
To: HITACHI, LTD.
Reel/Frame 019022/0462 →
Merger Sep 10, 2010
From: RENESAS TECHNOLOGY CORP.
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 024982/0148 →
Change of Address Nov 29, 2017
From: RENESAS ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 044928/0001 →