IP Library › Assignment 019047/0296
Patent Assignment
Reel/Frame 019047/0296

Security Agreement

Recorded: 2007-03-22 Received: 2007-03-22 Pages: 21
Assignors
PRECISION PHARMA SERVICES, INC.
Executed: 2006-12-06
TALECRIS BIOTHERAPEUTICS, INC.
Executed: 2006-12-06
TALECRIS PLASMA RESOURCES, INC.
Executed: 2006-12-06
Assignees
WELLS FARGO FOOTHILL, INC., AS COLLATERAL AGENT
2450 COLORADO AVE., SUITE 3000 WEST, SANTA MONICA, CA, 90404, UNITED STATES
WACHOVIA BANK, NATIONAL ASSOCIATION, AS ADMINISTRATIVE AGENT
1133 AVENUE OF THE AMERICA, NEW YORK, NY, 10036, UNITED STATES
Covered Properties (36)
Recombinantly Modified Plasmin
Application: 11/568,023 →
Apparatus and method for handling and opening a frangible container
Application: 11/470,390 →
Methods and compositions for treating herpes infections
Application: 11/367,772 →
Method of treatment and prophylaxis using IgM
Application: 60/763,422 →
Process for the Production of a Reversibly Inactive Acidified Plasmin Composition
Application: 10/692,105 →
Methods and Compositions for Treating Herpes Infections
Application: 10/656,781 →
Memory Device
Application: 10/413,829 →
Method of Thrombolysis by Local Delivery of Reversibly Inactivated Acidified Plasmin
Application: 10/280,444 →
System and Method to Facilitate Stabilization of Reference Voltage Signals in Memory Devices
Application: 10/223,486 →
Higher Program Vt and Faster Programming Rates Based on Improved Erase Methods
Application: 10/173,262 →
Process for the production of a reversibly inactive acidified plasmin composition
Application: 10/143,156 →
Reversibly inactivated acidified plasmin
Application: 10/143,112 →
Method of Thrombolysis by Local Delivery of Reversibly Inactivated Acidified Plasmin
Application: 10/143,157 →
Method of Using Pon-1 to Decrease Atheroma Formation
Application: 10/105,640 →
Method and Apparatus for Soft Program Verification in a Memory Device
Application: 10/050,650 →
Method and Apparatus for Pre-Charging Negative Pump Mos Regulation Capacitors
Application: 10/050,342 →
Diode Fabrication for Esd/Eos Protection
Application: 10/050,394 →
Charge Injection
Application: 10/050,483 →
Negative Pump Regulator Using Mos Capacitor
Application: 10/050,254 →
Source Side Sensing Scheme for Virtual Ground Read of Flash Eprom Array with Adjacent Bit Precharge
Application: 10/050,257 →
Method of Fabricating Double Densed Core Gates in Sonos Flash Memory
Application: 09/971,483 →
Salicided Gate for Virtual Ground Arrays
Application: 09/968,465 →
Salicided Gate for Virtual Ground Arrays
Application: 09/968,456 →
Modulated Charge Pump Which Uses an Analog to Digital Converter to Compensate for Supply Voltage Variations
Application: 09/892,189 →
Esd Implant Following Spacer Deposition
Application: 09/891,885 →
Erase Method for Dual Bit Virtual Ground Flash
Application: 09/886,861 →
Method of Manufacturing Spacer Etch Mask for Silicon-Oxide-Nitride-Oxide-Silicon (Sonos) Type Nonvolatile Memory
Application: 09/885,490 →
Low Column Leakage nor Flash Array-Double Cell Implementation
Application: 09/884,565 →
Novel Re-Oxidation Approach to Improve Peripheral Gate Oxide Integrity in a Tunnel Nitride Oxidation Process
Application: 09/879,738 →
Method and Apparatus for Boosting Bitlines for Low Vcc Read
Application: 09/873,643 →
System and Method to Facilitate Stabilization of Reference Voltage Signals in Memory Devices
Application: 09/824,166 →
Data retention characteristics as a result of high temperature bake
Application: 09/795,849 →
Single Bit Array Edges
Application: 09/795,865 →
Negative gate erase
Application: 09/795,856 →
Higher Program Vt and Faster Programming Rates Based on Improved Erase Methods
Application: 09/796,282 →
Tailored Erase Method Using Higher Program Vt and Higher Negative Gate Erase
Application: 09/795,854 →