IP Library Assignment 019538/0544
Patent Assignment
Reel/Frame 019538/0544

Assignment of Assignor's Interest

Recorded: 2007-07-03 Pages: 3
Assignors
KONISHI, HIDEAKI
Executed: 2007-03-05
SHIMIZU, RYUJI
Executed: 2007-03-08
HOJO, MASAYASU
Executed: 2007-04-17
ABE, HARUHIKO
Executed: 2007-03-23
MASUDA, SATOSHI
Executed: 2007-04-17
KOBAYASHI, NAOFUMI
Executed: 2007-04-17
Assignee
FUJITSU LIMITED
1-1, KAMIKODANAKA 4-CHOME, NAKAHARA-KU, KAWASAKI-SHI, KANAGAWA 211-8588, JAPAN
Covered Property (1)
Delay Failure Test Circuit
Patent: 7,640,124 →
Application: 11/717,769 →
Publication: US 2007/0288184
Related Assignments (3)
Other recorded transfers of the patent in this record — the chain of ownership.
Assignment of Assignor's Interest Dec 10, 2008
From: FUJITSU LIMITED
To: FUJITSU MICROELECTRONICS LIMITED
Reel/Frame 021985/0715 →
Change of Name Jul 27, 2010
From: FUJITSU MICROELECTRONICS LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 024794/0500 →
Assignment of Assignor's Interest Apr 27, 2015
From: FUJITSU SEMICONDUCTOR LIMITED
To: SOCIONEXT INC.
Reel/Frame 035508/0469 →