IP Library Assignment 021122/0462
Patent Assignment
Reel/Frame 021122/0462

Assignment of Assignor's Interest

Recorded: 2008-06-19 Pages: 8
Assignor
INVARIUM, INC.
Executed: 2008-06-04
Assignee
CADENCE DESIGN SYSTEMS, INC.
2655 SEELY AVENUE, SAN JOSE, CALIFORNIA, 95134-1931
Covered Property (1)
Method and System for Semiconductor Design Hierarchy Analysis and Transformation
Patent: 7,669,158 →
Application: 10/955,067 →
Publication: US 2006/0075371
Related Assignments (2)
Other recorded transfers of the patent in this record — the chain of ownership.
Assignment of Assignor's Interest Sep 30, 2004
From: KAMAT, VISHNU GOVIND
To: INVARIUM, INC.
Reel/Frame 015867/0400 →
Assignment of Assignor's Interest Mar 14, 2025
From: CADENCE DESIGN SYSTEMS, INC.
To: SILVACO, INC.
Reel/Frame 070519/0972 →