Assignment of Assignor's Interest

Recorded: 2008-09-30 Pages: 3

Assignor

YAMADA, KENTA

Executed: 2008-09-26

Assignee

NEC ELECTRONICS CORPORATION

1753 SHIMONUMABE, NAKAHARA-KU, KAWASAKI, KANAGAWA, 211-8668, JAPAN

Covered Property (1)

Method and apparatus for circuit simulation in view of stress exerted on MOS transistor

Application: 12/285,215 →

Publication: US 2009/0089037

Related Assignments (1)

Other recorded transfers of the patent in this record — the chain of ownership.