Method and apparatus for circuit simulation in view of stress exerted on MOS transistor
A circuit simulation method includes: generating graphical data indicating dimensions of a subject MOS transistor; calculating a parameter correction amount based on said graphical data; correcting a given transistor model parameter in response to said parameter correction amount; and performing circuit simulation of a circuit that includes said subject MOS transistor by using said corrected transistor model parameter. The parameter correction amount is calculated based on said graphical data by using arithmetic equations. The arithmetic equations include at least one stress model equation expressing a stress exerted on a channel region of a model MOS transistor. The stress model equation is suitably defined to simulate the stress exerted on the channel region.
1 . A circuit simulation method comprising:
generating graphical data indicating dimensions of a subject MOS transistor;
calculating a parameter correction amount based on said graphical data;
correcting a given transistor model parameter in response to said parameter correction amount; and
performing circuit simulation of a circuit that includes said subject MOS transistor by using said corrected transistor model parameter,
wherein said parameter correction amount is calculated based on said graphical data by using arithmetic equations,
wherein said arithmetic equations include at least one stress model equation expressing a stress exerted on a channel region of a model MOS transistor,
wherein said stress model equation is defined so that a magnitude of said stress monotonously decreases with an increase in an adjacent distance from an active region within which said channel region of said model MOS transistor is formed to an active region adjacent thereto, and converges to a constant value when said adjacent distance is infinitely large, and so that an absolute value of a differential coefficient of said stress with respect to said adjacent distance monotonously decreases with an increase in said adjacent distance, and converges to zero when said adjacent distance is infinitely large.
2 . The circuit simulation method according to claim 1 , wherein said stress model equation is defined so that a dependency of said magnitude of said stress on said adjacent distance varies in response to a width of said active region within which said channel region is formed.
3 . The circuit simulation method according to claim 2 , wherein said stress model equation is defined so that said magnitude of said stress monotonously decreases with an increase in said width of said active region within which said channel region is formed, and converges to a constant value when said width of said active region within which said channel region is formed is infinitely large.
4 . The circuit simulation method according to claim 1 , wherein said at least one stress model equation includes an equation representing a stress exerted in an in-plane direction of a substrate, and an equation representing a stress exerted in a vertical direction of said substrate.
5 . The circuit simulation method according to claim 4 , wherein said stress model equation represents said stress of said channel region of said model MOS transistor for a case where a layout pattern of said model MOS transistor is a basic pattern in which said active region is rectangular and has a length of LOD in a gate-length direction and a width of W, a gate is positioned at a center of said active region, distances PDX from said active region to active regions adjacent thereto in the gate-length direction are same and constant, and distances PDY from said active region to active regions adjacent thereto in the gate-width direction are same and constant, and
wherein said at least one stress model equation represents a stress σx exerted in a first direction which is an in-plane direction of the substrate, a stress σy exerted in a second direction which is an in-plane direction of the substrate and perpendicular to said first direction, and a stress σz exerted in a third direction which is the vertical direction of the substrate by the following equations:
σ x=σh ( LOD,PDX ),
σy=σh ( W,PDX ), and
σz=σv ( LOD,PDX )+σ v ( W,PDY ),
where σh and σv are functions defined with arguments Wd and Sd as follows:
σ
h
(
Wd
,
Sd
)
=
haa
Wd
+
hab
+
hac
Sd
+
(
hba
Wd
+
hbc
+
hbc
)
+
(
hca
Wd
+
hcb
+
hcc
)
,
σ
v
(
Wd
,
Sd
)
=
vaa
Wd
+
vab
+
vac
Sd
+
(
vba
Wd
+
vbc
+
vbc
)
+
(
vca
Wd
+
vcb
+
vcc
)
,
6 . The circuit simulation method according to claim 4 , wherein said stress model equation represents said stress of said channel region of said model MOS transistor for a case where a layout pattern of said model MOS transistor is a basic pattern in which said active region is rectangular and has a length of LOD in a gate-length direction and a width of W, a gate is positioned at a center of said active region, distances PDX from said active region to active regions adjacent thereto in the gate-length direction are same and constant, and distances PDY from said active region to active regions adjacent thereto in the gate-width direction are same and constant, and
wherein said at least one stress model equation represents a stress σx exerted in a first direction which is an in-plane direction of the substrate, a stress σy exerted in a second direction which is an in-plane direction of the substrate and perpendicular to said first direction, and a stress σz exerted in a third direction which is the vertical direction of the substrate by the following equations:
σ x=σhx ( LOD,PDX ),
σy=σhy ( W,PDX ), and
σz=σvx ( LOD,PDX )+σ vy ( W,PDY ),
where σhx, σhy, σvx and σvy are functions defined with arguments Wd and Sd as follows:
σ
hx
(
Wd
,
Sd
)
=
haax
Wd
+
habx
+
hacx
Sd
+
(
hbax
Wd
+
hbcx
+
hbcx
)
+
(
hcax
Wd
+
hcbx
+
hccx
)
,
σ
vx
(
Wd
,
Sd
)
=
vaax
Wd
+
vabx
+
vacx
Sd
+
(
vbax
Wd
+
vbcx
+
vbcx
)
+
(
vcax
Wd
+
vcbx
+
vccx
)
,
σ
hy
(
Wd
,
Sd
)
=
haay
Wd
+
haby
+
hacy
Sd
+
(
hbay
Wd
+
hbcy
+
hbcy
)
+
(
hcay
Wd
+
hcby
+
hccy
)
,
σ
vy
(
Wd
,
Sd
)
=
vaay
Wd
+
vaby
+
vacy
Sd
+
(
vbay
Wd
+
vbcy
+
vbcy
)
+
(
vcay
Wd
+
vcby
+
vccy
)
,
7 . The circuit simulation method according to claim 1 , wherein said calculating said parameter correction amount includes:
dividing a channel region of said subject MOS transistor into a plurality of channel portions based on changes in distances from a gate of said target MOS transistor to edges of an active region of said target MOS transistor; changes in gate-length direction distances which are distances from said active region of said target MOS transistor to first active regions adjacent thereto in a gate-length direction; and
changes in a gate-width direction distance which are distances from said active region of said target MOS transistor to second active regions adjacent thereto in a gate-width direction,
calculating partial parameter correction amounts which are parameter correction amounts defined for said respective channel portions; and
calculating said parameter correction amount from said partial parameter correction amounts.
8 . The circuit simulation method according to claim 7 , wherein said calculating said partial parameter correction amounts includes:
calculating parameter correction amounts by using a parameter correction amount calculation equation obtained for a case where a layout pattern of said model MOS transistor is a basic pattern in which said active region is rectangular, a gate is positioned at a center of said active region, distances from said active region to active regions adjacent thereto in the gate-length direction are same and constant, and distances from said active region to active regions adjacent thereto in the gate-width direction are same and constant, for said respective channel portions and for respective combinations of distances from said gate of said target MOS transistor to gate-length direction edges of said active region thereof which are positioned in said gate length direction with respect to said channel portions, distances from said first active regions to said gate-length direction edges, and directions from said second active regions to gate-width direction edges of said active region of said target MOS transistor which are positioned in said gate width direction with respect to said channel portions; and
calculating said partial parameter correction amounts through averaging said parameter correction amounts calculated for said respective combinations.
9 . The circuit simulation method according to claim 7 , wherein said parameter correction amount is calculated as a weighted sum of said partial parameter correction amounts with weighting coefficients determined in accordance with areas of said channel portions.
10 . A circuit simulation apparatus comprising:
a tool which generates graphical data indicating dimensions of a subject MOS transistor and calculates a parameter correction amount based on said graphical data; and
a circuit simulator which corrects a given transistor model parameter in response to said parameter correction amount, and performs circuit simulation of a circuit that includes said subject MOS transistor by using said corrected transistor model parameter,
wherein said parameter correction amount is calculated based on said graphical data by using arithmetic equations,
wherein said arithmetic equations include at least one stress model equation expressing a stress exerted on a channel region of a model MOS transistor,
wherein said stress model equation is defined so that a magnitude of said stress monotonously decreases with an increase in an adjacent distance from an active region within which said channel region of said model MOS transistor is formed to an active region adjacent thereto, and converges to a constant value when said adjacent distance is infinitely large, and so that an absolute value of a differential coefficient of said stress with respect to said adjacent distance monotonously decreases with an increase in said adjacent distance, and converges to zero when said adjacent distance is infinitely large.
11 . The circuit simulation apparatus according to claim 10 , wherein said tool divides a channel region of said subject MOS transistor into a plurality of channel portions based on changes in distances from a gate of said target MOS transistor to edges of an active region of said target MOS transistor; changes in gate-length direction distances which are distances from said active region of said target MOS transistor to first active regions adjacent thereto in a gate-length direction; and changes in a gate-width direction distance which are distances from said active region of said target MOS transistor to second active regions adjacent thereto in a gate-width direction;
wherein said tool calculates partial parameter correction amounts which are parameter correction amounts defined for said respective channel portions; and calculates said parameter correction amount from said partial parameter correction amounts.
12 . A computer-readable recording medium which records a program that when executed controls a computer to perform a method comprising:
generating graphical data indicating dimensions of a subject MOS transistor;
calculating a parameter correction amount based on said graphical data;
correcting a given transistor model parameter in response to said parameter correction amount; and
performing circuit simulation of a circuit that includes said subject MOS transistor by using said corrected transistor model parameter,
wherein said parameter correction amount is calculated based on said graphical data by using arithmetic equations,
wherein said arithmetic equations include at least one stress model equation expressing a stress exerted on a channel region of a model MOS transistor,
wherein said stress model equation is defined so that a magnitude of said stress monotonously decreases with an increase in an adjacent distance from an active region within which said channel region of said model MOS transistor is formed to an active region adjacent thereto, and converges to a constant value when said adjacent distance is infinitely large, and so that an absolute value of a differential coefficient of said stress with respect to said adjacent distance monotonously decreases with an increase in said adjacent distance, and converges to zero when said adjacent distance is infinitely large.
13 . The computer-readable recording medium according to claim 12 , wherein said calculating said parameter correction amount includes:
dividing a channel region of said subject MOS transistor into a plurality of channel portions based on changes in distances from a gate of said target MOS transistor to edges of an active region of said target MOS transistor; changes in gate-length direction distances which are distances from said active region of said target MOS transistor to first active regions adjacent thereto in a gate-length direction; and
changes in a gate-width direction distance which are distances from said active region of said target MOS transistor to second active regions adjacent thereto in a gate-width direction,
calculating partial parameter correction amounts which are parameter correction amounts defined for said respective channel portions; and
calculating said parameter correction amount from said partial parameter correction amounts.