Assignment of Assignor's Interest

Recorded: 2008-10-22 Pages: 4

Assignor

NAKAGAWA, NAOKO

Executed: 2008-10-08

Assignee

NEC ELECTRONICS CORPORATION

1753 SHIMONUMABE, NAKAHARA-KU, KAWASAKI, KANAGAWA, 211-8668, JAPAN

Covered Property (1)

Method for designing semiconductor device layout and layout design supporting apparatus

Application: 12/289,198 →

Publication: US 2009/0113374

Related Assignments (1)

Other recorded transfers of the patent in this record — the chain of ownership.