Method for designing semiconductor device layout and layout design supporting apparatus
In a layout design method for a semiconductor device having a hard macro, a netlist data of the semiconductor device and a hard macro data are read out from a storage section. An arrangement position of the hard macro is determined from the netlist data and the hard macro data, and an extension direction of an interconnection pattern in a specified area of a chip for the semiconductor device is determined based on arrangement restriction data. The interconnection pattern is arranged to extend in the determined extension direction in the specified area.
1 . A layout design method for a semiconductor device comprising a hard macro, comprising:
reading out a netlist data of the semiconductor device and a hard macro data from a storage section;
determining an arrangement position of said hard macro from the netlist data and the hard macro data;
determining an extension direction of an interconnection pattern in a specified area of a chip for the semiconductor device based on arrangement restriction data; and
arranging said interconnection pattern to extend in the determined extension direction in the specified area.
2 . The method according to claim 1 , further comprising:
storing said arrangement restriction data in said storage section as a part of said hard macro data in advance.
3 . The method according to claim 1 , further comprising:
supplying said arrangement restriction data.
4 . The method according to claim 1 , further comprising:
generating said arrangement restriction data.
5 . The method according to claim 1 , wherein said arrangement restriction data is provided for said hard macro.
6 . The method according to claim 1 , wherein said arrangement restriction data can be provided for each of interconnection layers of the chip.
7 . The method according to claim 1 , wherein said arrangement restriction data can be provided for an optional area of the chip.
8 . A layout design supporting apparatus for a semiconductor device comprising a hard macro, comprising:
a storage section configured to store a netlist data of the semiconductor device and a hard macro data; and
a processing section configured to read out the netlist data of the semiconductor device and the hard macro data from said storage section, to determine an arrangement position of said hard macro from the netlist data and the hard macro data, to determining an extension direction of an interconnection pattern in a specified area of a chip for the semiconductor device based on arrangement restriction data, and to arrange said interconnection pattern to extend in the determined extension direction in the specified area.
9 . The layout design supporting apparatus according to claim 8 , wherein said hard macro data includes said arrangement restriction data.
10 . The layout design supporting apparatus according to claim 8 , further comprising:
an input unit configured to supply said arrangement restriction data to said processing section.
11 . The layout design supporting apparatus according to claim 8 , wherein said processing section generates said arrangement restriction data.
12 . The layout design supporting apparatus according to claim 8 , wherein said arrangement restriction data is provided for said hard macro.
13 . The layout design supporting apparatus according to claim 8 , wherein said arrangement restriction data can be provided for each of interconnection layers of the chip.
14 . The layout design supporting apparatus according to claim 8 , wherein said arrangement restriction data can be provided for an optional area of the chip.
15 . A computer-readable recording medium in which code of a computer-readable program is recorded for a layout design method for a semiconductor device comprising a hard macro, said layout design method comprising:
reading out a netlist data of the semiconductor device and a hard macro data from a storage section;
determining an arrangement position of said hard macro from the netlist data and the hard macro data;
determining an extension direction of an interconnection pattern in a specified area of a chip for the semiconductor device based on arrangement restriction data; and
arranging said interconnection pattern to extend in the determined extension direction in the specified area.
16 . The computer-readable recording medium according to claim 15 , wherein said method further comprises:
storing said arrangement restriction data in said storage section as a part of said hard macro data in advance.
17 . The computer-readable recording medium according to claim 15 , wherein said method further comprises:
supplying said arrangement restriction data.
18 . The computer-readable recording medium according to claim 15 , wherein said method further comprises:
generating said arrangement restriction data.