Patent Assignment
Reel/Frame 022272/0054
Assignment of Assignor's Interest
Recorded: 2009-02-02
Pages: 2
Assignee
FUJITSU MICROELECTRONICS LIMITED
7-1, NISHI-SHINJUKU 2-CHOME, SHINJUKU-KU, TOKYO 163-0722, JAPAN
Covered Property
(1)
Logic Circuit Having Gated Clock Buffer
Related Assignments
(2)
Other recorded transfers of the patent in this record — the chain of ownership.