Logic circuit having gated clock buffer
A logic circuit includes a gated clock buffer including a control node, being set in either a first state or a second state in response to an input signal applied to the control node, outputting an input clock signal supplied as an output signal in the first state, and fixing an output signal to a constant value in the second state, a plurality of scan flip-flops receiving the output signal of the gated clock buffer, and included in at least part of a scan chain, and a combinational logic circuit coupled to at least one of the plurality of scan flip-flops.
1. A logic circuit, comprising:
a gated clock buffer including a control node, being set in either a first state or a second state in response to an input signal applied to the control node, outputting an input clock signal supplied as an output signal in the first state, and fixing an output signal to a constant value in the second state;
a plurality of scan flip-flops receiving the output signal of the gated clock buffer, and included in at least part of a scan chain; and
a combinational logic circuit coupled to at least one of the plurality of scan flip-flops,
wherein the input signal is controlled by a first signal in a first test operation and controlled by a second signal in a second test operation, the first signal assuming an enable value during a test using the scan chain, the second signal assuming an enable value during a scan shift in which the scan chain performs a shift operation, and the second signal assuming both an enable value and a disable value during a capture time in which the at least one of the plurality of scan flip-flops loads data from the combinational logic circuit.
2. The logic circuit as claimed in claim 1 , wherein the input signal is controlled by the first signal when a test is performed by setting a first test pattern in the plurality of scan flip-flops, and is controlled by the second signal when a test is performed by setting a second test pattern in the plurality of scan flip-flops.
3. The logic circuit as claimed in claim 1 , wherein the input signal is controlled by a third signal in a third test operation, and the third signal assumes a disable value during the capture time.
4. The logic circuit as claimed in claim 1 , wherein the second signal assumes the disable value during a portion of the capture time, and changes from the disable value to the enable value during a period in which the input clock signal supplied to the gated clock buffer is in an ON state.
5. The logic circuit as claimed in claim 4 , wherein the input signal is controlled by a signal switchable between the first signal, the second signal, and a third signal, the third signal assuming the enable value during the scan shift and assuming the disable value during the capture time.
6. The logic circuit as claimed in claim 1 , wherein the first signal and the second signal are supplied directly from an external source outside the logic circuit.
7. The logic circuit as claimed in claim 1 , wherein the first signal and the second signal are generated inside the logic circuit.
8. The logic circuit as claimed in claim 7 , wherein the signal that controls the input signal applied to the control node is an output signal of a TAP controller.
9. The logic circuit as claimed in claim 1 , wherein either one of the first signal and the second signal is selected in response to a value stored in a flip-flop included in the scan chain, the selected signal being used as the signal that controls the input signal applied to the control node.
10. A logic circuit, comprising:
a gated clock buffer including a control node, being set in either a first state or a second state in response to an input signal applied to the control node, outputting an input clock signal supplied as an output signal in the first state, and fixing an output signal to a constant value in the second state;
a plurality of scan flip-flops receiving the output signal of the gated clock buffer, and included in at least part of a scan chain; and
a combinational logic circuit coupled to at least one of the plurality of scan flip-flops,
wherein the input signal applied to the control node of the gated clock buffer is controlled by a control signal that assumes an enable value during a scan shift in which the scan chain performs a scan operation, and that assumes both an enable value and a disable value during a capture time, wherein the control signal changes from the disable value to the enable value during the capture time while the input clock signal supplied to the gated clock buffer is in an ON state, the capture time being a time period during which the at least one of the plurality of scan flip-flops loads data from the combinational logic circuit.