Assignment of Assignor's Interest

Recorded: 2009-09-10 Pages: 2

Assignor

KANAI, DAI

Executed: 2009-04-27

Assignee

FUJITSU MICROELECTRONICS LIMITED

7-1, NISHI-SHINJUKU 2-CHOME,, SHINJUKU-KU, TOKYO 163-0722, JAPAN

Covered Property (1)

Method of designing semiconductor device including density verification

Patent: 8,078,994 →

Application: 12/556,302 →

Publication: US 2010/0031208

Related Assignments (2)

Other recorded transfers of the patent in this record — the chain of ownership.