IP Library Assignment 025021/0449
Patent Assignment
Reel/Frame 025021/0449

Assignment of Assignor's Interest

Recorded: 2010-09-21 Pages: 3
Assignors
WATANABE, YUICHI
Executed: 2010-08-16
SHINADA, KIYOTAKA
Executed: 2010-08-16
KIMURA, YUUSHIN
Executed: 2010-08-16
GOTO, SHIGERU
Executed: 2010-08-23
TANDOU, YASUHIKO
Executed: 2010-08-30
TAKADA, EIJI
Executed: 2010-08-25
UESAKA, KOUJI
Executed: 2010-08-25
Assignees
FUJITSU LIMITED
1-1, KAMIKODANAKA 4-CHOME, NAKAHARA-KU, KAWASAKI-SHI, KANAGAWA, 211-8588, JAPAN
FUJITSU SEMICONDUCTOR LIMITED
2-10-23, SHIN-YOKOHAMA, KOHOKU-KU,, YOKOHAMA-SHI, KANAGAWA, 222-0033, JAPAN
Covered Property (1)
Semiconductor Testing Circuit, Semiconductor Testing Jig, Semiconductor Testing Apparatus, and Semiconductor Testing Method
Patent: 8,736,295 →
Application: 12/873,738 →
Publication: US 2011/0057681
Related Assignments (1)
Other recorded transfers of the patent in this record — the chain of ownership.
Assignment of Assignor's Interest Jun 30, 2015
From: FUJITSU SEMICONDUCTOR LIMITED
To: SOCIONEXT INC.
Reel/Frame 035935/0097 →