Patent Assignment
Reel/Frame 025142/0592
Security Agreement
Recorded: 2010-10-14
Pages: 7
Assignor
ATRENTA INC.
Executed: 2010-10-12
Assignee
SILICON VALLEY BANK
3003 TASMAN DRIVE, SANTA CLARA, CALIFORNIA, 95054
Covered Properties
(4)
Method for Compaction of Timing Exception Paths
Method and System for Equivalence Checking
Method for estimation of power consumption of scan chains of an integrated circuit for test
Application:
61/279,603 →
Apparatus and Method Thereof for a Hybrid Timing Exceptions Verification of an Integrated Circuit Design
Application:
61/373,511 →
Related Assignments
(5)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Sep 8, 2008
From: RAHIM, SOLAIMAN; BHATIA, MANISH; REJOUAN, HOUSSEINE
To: ATRENTA, INC.
Reel/Frame 021497/0364 →
Assignment of Assignor's Interest
May 26, 2010
From: RAHIM, SOLAIMAN; NALLA, PRADEEP KUMAR
To: ATRNETA, INC.
Reel/Frame 024443/0454 →
Corrective Assignment to Correct the Name of the Receiving Party (Assignee) from Atrneta, Inc. to Atrenta, Inc. Previously Recorded on Reel 024443 Frame 0454. Assignor(S) Hereby Confirms the Executed Assignment.
Jun 7, 2010
From: RAHIM, SOLAIMAN; NALLA, PRADEEP KUMAR
To: ATRENTA, INC.
Reel/Frame 024495/0484 →
Release of Security Interest
Sep 10, 2015
From: SILICON VALLEY BANK
To: ATRENTA INC.
Reel/Frame 036584/0644 →
Assignment of Assignor's Interest
Sep 25, 2015
From: ATRENTA INC.
To: SYNOPSYS, INC.
Reel/Frame 036687/0290 →