Patent Assignment
Reel/Frame 025223/0408
Assignment of Assignor's Interest
Recorded: 2010-10-31
Pages: 6
Assignors
AKHTER, MOHAMMAD SHAHANSHAH
Executed: 2010-10-29
WANG, ZIXIONG WILLIAM
Executed: 2010-10-29
BOND, DAVID CLIFTON
Executed: 2010-10-28
LUND, GREGORY EDWARD
Executed: 2010-10-29
Assignee
INTEGRATED DEVICE TECHNOLOGY, INC.
6024 SILVER CREEK VALLEY ROAD, SAN JOSE, CALIFORNIA, 95138
Covered Property
(1)
Method and Apparatus for a configurable packet routing, buffering and scheduling scheme to optimize throughput with deadlock prevention in SRIO-to-PCIe Bridges
Patent:
8,949,501 →
Application:
12/916,574 →
Related Assignments
(4)
Other recorded transfers of the patent in this record — the chain of ownership.
Security Agreement
Apr 5, 2017
From: INTEGRATED DEVICE TECHNOLOGY, INC.; GIGPEAK, INC.; MAGNUM SEMICONDUCTOR, INC.; ENDWAVE CORPORATION
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 042166/0431 →
Release of Security Interest
Mar 29, 2019
From: JPMORGAN CHASE BANK, N.A.
To: INTEGRATED DEVICE TECHNOLOGY, INC.; GIGPEAK, INC.; CHIPX, INCORPORATED; ENDWAVE CORPORATION
Reel/Frame 048746/0001 →
Merger
Apr 15, 2025
From: INTEGRATED DEVICE TECHNOLOGY, INC.
To: RENESAS ELECTRONICS AMERICA INC.
Reel/Frame 070851/0391 →
Assignment of Assignor's Interest
Apr 16, 2025
From: RENESAS ELECTRONICS AMERICA INC.
To: AXIRO SEMICONDUCTOR INC.
Reel/Frame 070864/0142 →