Assignment of Assignor's Interest

Recorded: 2011-08-18 Pages: 3

Assignor

ANDOU, TETSUO

Executed: 2008-11-21

Assignee

NEC ELECTRONICS CORPORATION

1753 SHIMONUMABE, NAKAHARA-KU, KAWASAKI KANAGAWA 211-8668, JAPAN

Covered Property (1)

Layout design method of semiconductor integrated circuit by using soft macro

Application: 12/292,802 →

Publication: US 2009/0144687

Related Assignments (1)

Other recorded transfers of the patent in this record — the chain of ownership.