IP Library › Assignment 027727/0212
Patent Assignment
Reel/Frame 027727/0212

Assignment of Assignor's Interest

Recorded: 2012-02-16 Pages: 63
Assignors
SILICON GRAPHICS, INC. ET AL.
Executed: 2009-05-08
SGI INTERNATIONAL, INC.
Executed: 2012-02-08
Assignee
SILICON GRAPHICS INTERNATIONAL, CORP.
46600 LANDING PARKWAY, FREMONT, CALIFORNIA, 94538-6420
Covered Properties (111)
Miniature Controlled-Impedance Transmission Line Cable and Method of Manufacture
Patent: 5,015,800 →
Application: 07/454,022 →
Cluster Architecture for a Highly Parallel Scalar/Vector Mulriprocessor System
Patent: 5,197,130 →
Application: 07/459,083 →
Method and Apparatus for Non-Sequential Resource Access
Patent: 5,208,914 →
Application: 07/535,786 →
Vertical Semiconductor Interconnection Method and Structure
Patent: 5,041,903 →
Application: 07/535,837 →
Control and Maintenance Subsystem Network for Use with a Multiprocessor Computer System
Patent: 5,253,359 →
Application: 07/535,901 →
Distributed Architecture for Input/Output for a Multiprocessor System
Patent: 5,168,547 →
Application: 07/536,182 →
Dedicated Centralized Signaling Mechanism for Selectively Signaling Devices in a Multiprocessor System
Patent: 5,239,629 →
Application: 07/536,192 →
Method and Apparatus for a Special Purpose Arithmetic Boolean Unit
Patent: 5,175,862 →
Application: 07/536,197 →
Global Registers for a Multiprocessor System
Patent: 5,165,038 →
Application: 07/536,198 →
Clock Distribution Apparatus and Processes Using Electrical and Optical Delay Lines Particularly Useful in Multiprocessor Systems
Patent: 5,293,626 →
Application: 07/536,270 →
Packaging Architecture for a Highly Parallel Multiprocessor System
Patent: 5,251,097 →
Application: 07/536,395 →
Method and Apparatus for a Multiple Request Toggling Priority System
Patent: 5,168,570 →
Application: 07/536,417 →
System and Method for Controlling a Highly Parallel Multiprocessor Using an Anarchy Based Scheduler for Parallel Execution Thread Scheduling
Patent: 5,179,702 →
Application: 07/537,466 →
Method and Apparatus for Single Step Clocking on Signal Paths Longer Than a Clock Cycle
Patent: 5,055,707 →
Application: 07/568,169 →
System for Communicating Among Processors Having Different Speeds
Patent: 5,202,988 →
Application: 07/571,951 →
Computer with Integrated Hierarchical Reprsentation (Ihr) of Program Wherein Ihr File Is Available for Debugging and Optimizing During Target Execution
Patent: 5,175,856 →
Application: 07/572,043 →
Method for Efficient Non-Virtual Main Memory Management
Patent: 5,159,678 →
Application: 07/572,045 →
System for Distributed Multiprocessor Communication
Patent: 5,434,970 →
Application: 07/655,296 →
Transmission Line with Fluid-Permeable Jacket
Patent: 5,142,100 →
Application: 07/694,467 →
Memory Range Monitoring Apparatus for a Multiprocessor Computer System
Patent: 5,295,260 →
Application: 07/708,461 →
Method and Apparatus for Memory Access in a Matrix Processor Computer
Patent: 6,282,583 →
Application: 07/710,146 →
Metallized Connector Block
Patent: 5,211,567 →
Application: 07/725,007 →
Method of Fabricating Silicon-Based Carriers
Patent: 5,196,377 →
Application: 07/747,523 →
A Parallel Vector Processing System for Individual and Braodcast Distribution of Operands and Control Information
Patent: 5,226,171 →
Application: 07/802,643 →
Clock Pulse Measuring and Deskewing System and Process
Patent: 5,329,188 →
Application: 07/803,926 →
Multilayer Interconnect System for an Area Array Interconnection Using Solid State Diffusion
Patent: 5,276,955 →
Application: 07/868,531 →
Solid State Storage Device
Patent: 5,321,697 →
Application: 07/890,026 →
Fast Interrupt Mechanism for a Interrupting Processors in Parallel in a Multiprocessor System Wherein Processors Are Assigned Process Id Numbers
Patent: 5,193,187 →
Application: 07/898,387 →
Method and Apparatus for a Unified Parallel Processing Architecture
Patent: 5,428,803 →
Application: 07/912,964 →
High Performance Mantissa Divider
Patent: 5,258,944 →
Application: 07/938,715 →
Clock Start Up Stabilization for Computer Systems
Patent: 5,355,397 →
Application: 07/950,628 →
Dual Level Scheduling of Processes to Multiple Parallel Regions of a Multi-Threaded Program on a Tightly Coupled Multiprocessor Computer System
Patent: 5,339,415 →
Application: 07/973,598 →
Apparatus for Cooling Daughter Boards
Patent: 5,343,359 →
Application: 07/983,086 →
Direction Order Priority Routing of Packets Between Nodes in a Networked System
Patent: 5,533,198 →
Application: 07/983,979 →
Method and Apparatus for User Side Scheduling in a Multiprocessor Operating System Program That Implements Distributive Scheduling of Processes
Patent: 6,195,676 →
Application: 08/003,000 →
Control System and Method for Direct Execution of Software Application Information Models Without Code Generation
Patent: 5,390,330 →
Application: 08/016,430 →
Optical Clock Distribution System
Patent: 5,537,498 →
Application: 08/027,049 →
Printed Circuit Board with Cooling Monitoring System
Patent: 5,281,026 →
Application: 08/056,650 →
Multiprocessing System Using Indirect Addressing to Access Respective Local Semaphore Registers Bits for Setting the Bit or Branching If the Bit Is Set
Patent: 5,367,690 →
Application: 08/129,437 →
Method and Apparatus for Locking Shared Memory Locations in Multiprocessing Systems
Patent: 5,535,365 →
Application: 08/141,259 →
Configurable Spare Memory Chips
Patent: 5,392,292 →
Application: 08/149,967 →
System and Method of Addressing Distributed Memory Within a Massively Parallel Processing System
Patent: 5,765,181 →
Application: 08/165,118 →
Barrier Synchronization for Distributed Memory Massively Parallel Processing Systems
Patent: 5,434,995 →
Application: 08/165,265 →
System for Allocating Messages Between Virtual Channels to Avoid Deadlock and to Optimize the Amount of Message Traffic on Each Type of Virtual Channel
Patent: 5,583,990 →
Application: 08/165,266 →
Method for the Dynamic Allocation of Array Sizes in a Multiprocessor System
Patent: 5,586,325 →
Application: 08/165,379 →
Recursive Address Centrifuge for Distributed Memory Massively Parallel Processing Systems
Patent: 5,696,922 →
Application: 08/165,388 →
Repetitive Signal Detector for Preventing Thermal Runaway
Patent: 5,418,481 →
Application: 08/165,747 →
Virtual to Logical to Physical Address Translation for Distributed Memory Massively Parallel Processing Systems
Patent: 5,784,706 →
Application: 08/165,814 →
Method of Managing Distributed Memory Within a Massively Parallel Processing System
Patent: 5,566,321 →
Application: 08/166,293 →
Messaging Facility with Hardware Tail Pointer and Software Implemented Head Pointer Message Queue for Distributed Memory Massively Parallel Processing System
Patent: 5,581,705 →
Application: 08/166,443 →
Method for the Dynamic Allocation of Page Sizes in Virtual Memory
Patent: 5,802,341 →
Application: 08/166,451 →
Interleaved Memory Access System Having Variable-Sized Segments Logical Address Spaces and Means for Dividing/Mapping Physical Address into Higher and Lower Order Addresses
Patent: 5,561,784 →
Application: 08/268,660 →
Extendible Clock Mechanism
Patent: 5,625,831 →
Application: 08/331,730 →
Stream Buffers for High-Performance Computer Memory Systems
Patent: 5,761,706 →
Application: 08/333,133 →
Apparatus and Method for Testing Using Clocked Test Access Port Controller for Level Sensitive Scan Designs
Patent: 6,173,428 →
Application: 08/340,238 →
Method and Apparatus for Accessing Global Registers in a Multiprocessor System
Patent: 5,524,255 →
Application: 08/379,123 →
Boundary Scan Testing Using Clocked Signal
Patent: 5,487,074 →
Application: 08/406,571 →
Adaptive Routing Mechanism for Torus Interconnection Network
Patent: 5,701,416 →
Application: 08/421,566 →
System for Randomly Modifying Virtual Channel Allocation and Accepting the Random Modification Based on the Cost Function
Patent: 5,659,796 →
Application: 08/422,072 →
Barrier and Eureka Synchronization Architecture for Multiprocessors
Patent: 5,721,921 →
Application: 08/450,251 →
Configuring of Networked System to Permit Replacement of Failed Nodes and Selection of Alternate Paths
Patent: 5,689,646 →
Application: 08/541,803 →
Virtual Maintenance Network in Multiprocessing System Having a Non- Flow Controlled Virtual Maintenance Channel
Patent: 6,055,618 →
Application: 08/550,992 →
Transparent Relocation of Real Memory Addresses in the Main Memory of a Data Processor
Patent: 5,765,198 →
Application: 08/595,528 →
Daughter Card Assembly
Patent: 5,761,043 →
Application: 08/604,839 →
Air or Liquid Cooled Computer Module Cold Plate
Patent: 6,305,463 →
Application: 08/604,841 →
Method and Apparatus for Cooling Daughter Card Modules
Patent: 5,801,924 →
Application: 08/604,888 →
Cooling Cap Method and Apparatus for Tab Packaged Integrated Circuits
Patent: 5,805,418 →
Application: 08/604,918 →
Cooling Approach for High Power Integrated Circuits Mounted on Printed Circuit Boards
Patent: 5,768,104 →
Application: 08/605,355 →
Massively Parallel Processing System Using Two Data Paths: One Connecting Router Circuit to the Interconnect Network and the Other Connecting Router Circuit to I/O Controller
Patent: 5,864,738 →
Application: 08/614,859 →
System and Method for Fault-Tolerant Transmission of Data Within a Dual Ring Network
Patent: 6,233,704 →
Application: 08/614,860 →
Using External Registers to Extend Memory Reference Capabilities of a Microprocessor
Patent: 5,835,925 →
Application: 08/615,671 →
Messaging in Distributed Memory Multiprocessing System Having Shell Circuitry for Atomic Control of Message Storage Queue's Tail Pointer Structure in Local Memory
Patent: 5,841,973 →
Application: 08/615,694 →
Adaptive Congestion Control Mechanism for Modular Computer Networks
Patent: 5,748,900 →
Application: 08/615,700 →
Raid-5 Parity Generation and Data Reconstruction
Patent: 5,805,788 →
Application: 08/650,336 →
Method and Apparatus for Adjusting the Power Supply Voltage Provided to a Microprocessor
Patent: 5,694,028 →
Application: 08/650,337 →
A System for Arbitrating Packetized Data from the Network to the Peripheral Resources and Prioritizing the Dispatching of Packets Onto the Network
Patent: 5,761,534 →
Application: 08/650,630 →
A Raid System Using I/O Buffer Segment to Temporary Store Striped and Parity Data and Connecting All Disk Drives via a Single Time Multiplexed Network
Patent: 5,862,313 →
Application: 08/650,632 →
Networked Multiprocessor System with Global Distributed Memory and Block Transfer Engine
Patent: 5,797,035 →
Application: 08/661,908 →
Multiprocessor Computer System with Interleaved Processing Element Nodes
Patent: 5,737,628 →
Application: 08/662,868 →
Method and Apparatus for Removing Power-of-Two Restrictions on Distributed Addressing
Patent: 5,900,023 →
Application: 08/673,436 →
Density Dependent Vector Mask Operation Control Apparatus and Method
Patent: 5,940,625 →
Application: 08/706,808 →
Recursive Address Centrifuge for Distributed Memory Massively Parallel Processing Systems
Patent: 6,119,198 →
Application: 08/889,251 →
Precise Detection of Errors Using Hardware Watchpoint Mechanism
Patent: 5,987,626 →
Application: 08/920,177 →
Stop Align Lateral Module to Module Interconnect
Patent: 6,116,915 →
Application: 08/927,359 →
System and Method for Distributed Multiprocessor Communications
Patent: 5,920,714 →
Application: 08/927,507 →
Adaptive Bandwidth Sharing
Patent: 6,205,119 →
Application: 08/931,565 →
Demateable, Compliant, Area Array Interconnect
Patent: 6,142,789 →
Application: 08/934,973 →
Adaptive Congestion Control Mechanism for Modular Computer Networks
Patent: 5,958,017 →
Application: 08/935,667 →
Porous Metal Heat Sink
Patent: 6,018,459 →
Application: 08/971,179 →
Multiprocessor Computer System and Method for Maintaining Cache Coherence Utilizing a Multi-Demensional Cache Coherence Directory Structure
Patent: 6,633,958 →
Application: 08/971,184 →
Spacial Derivative Bus Encoder and Decoder
Patent: 6,480,548 →
Application: 08/971,185 →
Router Table Lookup Mechanism
Patent: 5,970,232 →
Application: 08/971,587 →
Hybrid Hypercube/Torus Architecture
Patent: 6,230,252 →
Application: 08/971,588 →
Virtual Channel Assignment in Large Torus Systems
Patent: 6,101,181 →
Application: 08/971,591 →
Serialized Race-Free Virtual Barrier Network
Patent: 6,085,303 →
Application: 08/972,010 →
Interleaving Memory in Distributed Vector Architecture Multiprocessor System
Patent: 5,913,069 →
Application: 08/987,948 →
Distributed Vector Architecture
Patent: 5,946,496 →
Application: 08/988,524 →
Message Buffering for a Computer-Based Network
Patent: 6,256,677 →
Application: 08/991,233 →
Method of Handling Arbitrary Size Message Queues in Which a Message Is Written into an Aligned Block of External Registers Within a Plurality of External Registers
Patent: 6,029,212 →
Application: 09/006,449 →
The Fabrication of Test Logic for Level Sensitive Scan on a Circuit
Patent: 6,092,226 →
Application: 09/021,651 →
Diamond-Based Transformers and Power Convertors
Patent: 6,181,231 →
Application: 09/055,554 →
System and for Stacking of Integrated Circuit Packages
Patent: 6,172,874 →
Application: 09/055,677 →
Large Area, Multi-Device Heat Pipe for Stacked Mcm-Based Systems
Patent: 6,055,157 →
Application: 09/056,037 →
Method and Apparatus for Processing a Set of Data Values with Plural Processing Units Using Mask Bits Generated by Other Processing Units
Patent: 6,308,250 →
Application: 09/103,201 →
Eigen-Mode Encoding of Signals in a Data Group
Patent: 6,226,330 →
Application: 09/118,158 →
Cooling Cap Method and Apparatus for Tab Packaged Integrated Circuit
Patent: 5,963,428 →
Application: 09/136,908 →
System and Method for Fast Barrier Synchronization
Patent: 6,216,174 →
Application: 09/162,673 →
Array Address and Loop Alignment Calculations
Patent: 6,128,639 →
Application: 09/174,862 →
High Performance Gas Cooling System and Method
Patent: 6,167,947 →
Application: 09/215,531 →
Age-Based Network Arbitration System and Method
Patent: 6,674,720 →
Application: 09/408,778 →
Spacial Derivative Bus Encoder and Decoder
Patent: 7,167,523 →
Application: 10/171,095 →
Publication: US 2003/0072378
Related Assignments (25)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignors Interest. Dec 20, 1989
From: VAUPOTIC, GREGORY P.; BECK, DORIS A.; CHY, SOKHA
To: PRECISION INTERCONNECT CORPORATION
Reel/Frame 005204/0685 →
Assignment of Assignors Interest. Feb 22, 1990
From: CHEN, STEVE S.; SIMMONS, FREDERICK J.; SPIX, GEORGE A.; WILSON, JIMMIE R.
To: SUPERCOMPUTER SYSTEMS LIMITED PARTNERSHIP
Reel/Frame 005247/0997 →
Assignment of Assignors Interest. Jun 8, 1990
From: PRIEST, EDWARD C.; BARBER, STEVEN C.; SHINTAKU, KEN; HANSON, DAVID A.
To: SUPERCOMPUTER SYSTEMS LIMITED PARTNERSHIP
Reel/Frame 005344/0274 →
Assignment of Assignors Interest. Jun 11, 1990
From: MILLER, EDWARD C.; SPIX, GEORGE A.; SCHOOLER, ANTHONY R.; BEARD, DOUGLAS R.
To: SUPERCOMPUTER SYSTEMS LIMITED PARTNERSHIP, A LIMITED PARTNERSHIP OF DE.
Reel/Frame 005352/0415 →
Assignment of Assignors Interest. Jun 11, 1990
From: BEARD, DOUGLAS R.; SPIX, GEORGE A.; MILLER, EDWARD C.; STROUT, ROBERT E. II
To: SUPERCOMPUTER SYSTEMS LIMITED PARTNERSHIP, A LIMITED PARTNERSHIP OF DE
Reel/Frame 005351/0427 →
Assignment of Assignors Interest. Jun 11, 1990
From: WILSON, JIMMIE R.; BEARD, DOUGLAS R.; CHEN, STEVE S.; ECKERT, ROGER E.
To: SUPERCOMPUTER SYSTEMS LIMITED PARTNERSHIP, A LIMITED PARTNERSHIP OF DE
Reel/Frame 005331/0882 →
Assignment of Assignors Interest. Jun 11, 1990
From: ECKERT, ROGER E.; PHELPS, ANDREW E.
To: SUPERCOMPUTER SYSTEMS LIMITED PARTNERSHIP, A LIMITED PARTNERSHIP OF DE
Reel/Frame 005375/0451 →
Assignment of Assignors Interest. Jun 11, 1990
From: PHELPS, ANDREW E.; BEARD, DOUGLAS R.; WOODSMANSEE, MICHAEL A.
To: SUPERCOMPUTER SYSTEMS LIMITED PARTNERSHIP, 1414 W. HAMILTON AVE., EAU CLAIRE, WI 54701 A LIMITED PARTNERSHIP OF DE
Reel/Frame 005347/0863 →
Assignment of Assignors Interest. Jun 11, 1990
From: SPIX, GEORGE A.; COLLIER, GLEN L.; THROOP, G. JOSEPH; CLOUNCH, DAVID L.
To: SUPERCOMPUTER SYSTEMS LIMITED PARTNERSHIP, A LIMITED PARTNERSHIP OF DE.
Reel/Frame 005352/0409 →
Assignment of Assignors Interest. Aug 13, 1990
From: MILLERICK, MICHAEL A.
To: NATIONAL SEMICONDUCTOR CORPORATION; SUPERCOMPUTER SYSTEMS LIMITED PARTNERSHIP, INC.
Reel/Frame 005414/0131 →
Assignment of Assignors Interest. Aug 13, 1990
From: BEARD, DOUGLAS R.
To: SUPERCOMPUTER SYSTEMS LIMITED PARTNERSHIP
Reel/Frame 005459/0073 →
Assignment of Assignors Interest. Aug 13, 1990
From: PAUTSCH, GREGORY W.
To: NATIONAL SEMICONDUCTOR CORPORATION; SUPERCOMPUTER SYSTEMS LIMITED PARTNERSHIP, INC.
Reel/Frame 005414/0135 →
Assignment of Assignors Interest. Aug 23, 1990
From: SPIX, GEORGE A.; GAERTNER, GREGORY G.; WENGELSKI, DIANE M.; THOMPSON, KEITH J.
To: SUPERCOMPUTER SYSTEMS LIMITED PARTNERSHIP, A LIMITED PARTNERSHIP UNDER THE LAW OF DE
Reel/Frame 005429/0544 →
Assignment of Assignors Interest. Aug 23, 1990
From: SPIX, GEORGE A.; WENGELSKI, DIANE M.; HAWKINSON, STUART W.; JOHNSON, MARK D.
To: SUPERCOMPUTER SYSTEMS LIMITED PARTNERSHIP
Reel/Frame 005421/0288 →
Assignment of Assignors Interest. Aug 23, 1990
From: WENGELSKI, DIANE M.; GAERTNER, GREGORY G.
To: SUPERCOMPUTER SYSTEMS LIMITED PARTNERSHIP
Reel/Frame 005423/0864 →
Assignment of Assignors Interest. Aug 23, 1990
From: SIMMONS, FREDERICK J.; CHEN, STEVE S.; PAUTSCH, GREG W.; RABSKA, MICHAEL H.
To: SUPERCOMPUTER SYSTEMS LIMITED PARTNERSHIP
Reel/Frame 005462/0638 →
Assignment of Assignors Interest. Sep 27, 1990
From: MILLER, EDWARD C.; CHEN, STEVE S.; SIMMONS, FREDERICK J.; SPIX, GEORGE A.
To: SUPERCOMPUTER SYSTEMS LIMITED PARTNERSHIP
Reel/Frame 005450/0879 →
Assignment of Assignors Interest. Oct 9, 1990
From: PRECISION INTERCONNECT CORPORATION
To: SUPERCOMPUTER SYSTEMS LIMITED PARTNERSHIP
Reel/Frame 005461/0481 →
Assignment of Assignors Interest. Oct 22, 1990
From: VAN DYKE, DON A.; CRAMER, TIMOTHY J.; RASBOLD, JAMES C.; O'HAIR, KELLY T.
To: SUPERCOMPUTER SYSTEMS LIMITED PARTNERSHIP, A LIMITED PARTNERSHIP OF DELAWARE
Reel/Frame 005494/0714 →
Assignment of Assignors Interest. Apr 8, 1991
From: SCHIFFLEGER, ALAN J.
To: CRAY RESEARCH, INC.
Reel/Frame 005714/0997 →
Assignment of Assignors Interest. May 1, 1991
From: VAUPOTIC, GREGORY P.
To: PRECISION INTERCONNECT CORPORATION
Reel/Frame 005703/0526 →
Assignment of Assignors Interest. Jun 4, 1991
From: PINCUS, PHILIP A.; CHARLESWORTH, ALAN E.; CARLILE, BRADLEY R.
To: FLOATING POINT SYSTEMS INC.
Reel/Frame 005730/0908 →
Assignment of Assignors Interest. Jul 12, 1991
From: PRIBNOW, RICHARD D.
To: CRAY RESEARCH, INC., A CORP. OF DE
Reel/Frame 005787/0992 →
Assignment of Assignors Interest. Aug 23, 1991
From: NEUMANN, EUGENE F.; AUGUST, MELVIN C.; BOWEN, STEPHEN A.; PAUTSCH, GREGORY W.
To: CRAY RESEARCH, INC. A CORPORATION OF DE
Reel/Frame 005830/0320 →
Assignment of Assignors Interest. Oct 11, 1991
From: WAGNER, JOHN J.; THOMAS, CHOJNACKI P.; EBERLEIN, DELVIN D.
To: CRAY RESEARCH, INC. A CORPORATION OF DE
Reel/Frame 005882/0288 →