IP Library Assignment 029719/0912
Patent Assignment
Reel/Frame 029719/0912

Assignment of Assignor's Interest

Recorded: 2013-01-30 Pages: 9
Assignors
ANDREEV, ALEXANDER
Executed: 2013-01-14
GRIBOK, SERGEY
Executed: 2012-10-25
SCEPANOVIC, RANKO L.
Executed: 2012-10-26
TAN, PHEY-CHUIN
Executed: 2012-10-24
KUNG, CHEE-WEI
Executed: 2012-10-24
Assignee
EASIC CORPORATION
2585 AUGUSTINE DRIVE, SUITE 100, SANTA CLARA, CALIFORNIA, 95054
Covered Property (1)
Via-Configurable High-Performance Logic Block Involving Transistor Chains
Patent: 8,957,398 →
Application: 13/649,510 →
Publication: US 2014/0028348
Related Assignments (2)
Other recorded transfers of the patent in this record — the chain of ownership.
Assignment of Assignor's Interest Mar 11, 2019
From: EASIC CORPORATION
To: INTEL CORPORATION
Reel/Frame 048559/0162 →
Assignment of Assignor's Interest Sep 18, 2025
From: INTEL CORPORATION
To: INTEL NDTM US LLC
Reel/Frame 072293/0744 →