IP Library › Assignment 034176/0162
Patent Assignment
Reel/Frame 034176/0162

RELEASE OF SECURITY INTEREST

Recorded: 2014-11-05 Received: 2014-11-05 Pages: 14
Assignor
Assignee
VITESSE SEMICONDUCTOR CORPORATION
4721 CALLE CARGA, CAMARILLO, CA, 93012, UNITED STATES
Covered Applications (67)
ADAPTIVE DATA RECOVERY SYSTEM WITH INPUT SIGNAL EQUALIZATION
App. No. 12/366,544
→
CONTINUOUSLY INTERLEAVED ERROR CORRECTION
App. No. 12/270,774
→
DIFFERENTIAL VOLTAGE MODE DRIVER AND DIGITAL IMPEDANCE CALIBERATION OF SAME
App. No. 12/239,418
→
FUSES FOR MEMORY REPAIR
App. No. 12/207,321
→
SYSTEM AND METHOD FOR DETECTING EARLY LINK FAILURE IN AN ETHERNET NETWORK
App. No. 12/029,195
→
SYSTEM AND METHOD FOR SQUELCHING A RECOVERED CLOCK IN AN ETHERNET NETWORK
App. No. 12/029,230
→
METHOD AND APPARATUS FOR IMPROVED HIGH-SPEED ADAPTIVE EQUALIZATION
App. No. 11/943,569
→
HIGH-SPEED DATA INTERFACE FOR CONNECTING NETWORK DEVICES
App. No. 11/555,168
→
MAINTAINING FILTERING DATABASE CONSISTENCY
App. No. 11/508,361
→
DIFFERENTIAL OPTO-ELECTRONICS TRANSMITTER
App. No. 11/330,497
→
CROSSPOINT SWITCH WITH SWITCH MATRIX MODULE
App. No. 11/231,320
→
DIGITAL AUTOMATIC POWER CONTROL LOOP FOR CONTINUOUS AND BURST MODE APPLICATIONS
App. No. 11/221,609
→
DATA DE-SKEW METHOD AND SYSTEM
App. No. 11/218,331
→
VARIABLE BANDWIDTH TRANSIMPEDANCE AMPLIFIER WITH ONE-WIRE INTERFACE
App. No. 11/060,061
→
ADAPTIVE EQUALIZATION WITH GROUP DELAY
App. No. 11/029,297
→
POWER AND AREA EFFICIENT ADAPTIVE EQUALIZATION
App. No. 10/872,108
→
INTEGRATED CIRCUIT IMPLEMENTATION FOR POWER AND AREA EFFICIENT ADAPTIVE EQUALIZATION
App. No. 10/872,307
→
METHOD AND APPARATUS FOR CONFIGURING THE OPERATION OF AN INTEGRATED CIRCUIT
App. No. 10/852,586
→
OPTICAL DISPERSION CORRECTION IN TRANSIMPEDANCE AMPLIFIERS
App. No. 10/841,948
→
METHOD AND APPARATUS FOR IMPROVED HIGH-SPEED FEC ADAPTIVE EQUALIZATION
App. No. 10/810,271
→
OUTPUT CLOCK ADJUSTMENT FOR A DIGITAL I/O BETWEEN PHYSICAL LAYER DEVICE AND MEDIA ACCESS CONTROLLER
App. No. 10/754,204
→
SWITCHING MODE REGULATOR FOR SFP ETHERNET ADAPTOR
App. No. 10/754,250
→
METHOD FOR DETECTING LINK PARTNER STATE DURING AUTO NEGOTIATION AND SWITCHING LOCAL STATE TO ESTABLISH LINK
App. No. 10/754,256
→
DATA LOOP PORT ACCELERATION CIRCUIT
App. No. 10/724,957
→
METHOD OF OVERTONE SELECTION AND LEVEL CONTROL IN AN INTEGRATED CIRCUIT CMOS NEGATIVE RESISTANCE OSCILLATOR TO ACHIEVE LOW JITTER
App. No. 10/721,910
→
METHOD AND APPARATUS FOR IMPROVED HIGH-SPEED ADAPTIVE EQUALIZATION
App. No. 10/677,123
→
MEANS AND A METHOD FOR SWITCHING DATA PACKETS OR FRAMES
App. No. 10/617,884
→
Packet forwarding method and system
App. No. 10/429,267
→
GBIT/S TRANSCEIVER WITH BUILT-IN SELF TEST FEATURES
App. No. 10/428,326
→
ON-CHIP CALIBRATED SOURCE TERMINATION FOR VOLTAGE MODE DRIVER AND METHOD OF CALIBRATION THEREOF
App. No. 10/411,993
→
SELF-ALIGNED BIPOLAR TRANSISTOR
App. No. 10/364,075
→
APPARATUS AND METHOD FOR INTER-CHIP OR CHIP-TO-SUBSTRATE CONNECTION WITH A SUB-CARRIER
App. No. 10/308,458
→
FAST LOCKING CLOCK AND DATA RECOVERY UNIT
App. No. 10/295,276
→
ADJUSTMENT OF A CLOCK DUTY CYCLE
App. No. 10/282,398
→
MULTIPLE CHANNEL ADAPTIVE DATA RECOVERY SYSTEM
App. No. 10/266,383
→
MULTIPLE ELEMENT CONTROLLED OPTICAL COUPLING
App. No. 10/222,341
→
TRANSFORMERLESS ETHERNET CONTROLLER
App. No. 10/189,619
→
DUAL-MIXER LOSS OF SIGNAL DETECTION CIRCUIT
App. No. 10/159,648
→
CONTROL TECHNIQUES AND DEVICES FOR AN OPTICAL SWITCH ARRAY
App. No. 10/150,531
→
PRECISE PHASE DETECTOR
App. No. 10/145,412
→
A SYSTEM AND A METHOD FOR MAINTAINING QUALITY OF SERVICE THROUGH A CONGESTED NETWORK
App. No. 10/139,338
→
DATA SWITCHING SYSTEM
App. No. 10/138,496
→
CLOCK AND DATA RECOVERY WITH A FEEDBACK LOOP TO ADJUST THE SLICE LEVEL OF AN INPUT SAMPLING CIRCUIT
App. No. 10/119,545
→
HIGH BANDWIDTH CLOCK BUFFER
App. No. 10/099,668
→
METHOD OF CONTROLLING THE TURN OFF CHARACTERISTICS OF A VCSEL DIODE
App. No. 10/096,739
→
TIME BASED PACKET SCHEDULING AND SORTING SYSTEM
App. No. 10/096,442
→
METHOD AND APPARATUS FOR SCHEDULING DATA ON A MEDIUM
App. No. 10/081,152
→
HIGH SPEED CROSS POINT SWITCH ROUTING CIRCUIT WITH WORD-SYNCHRONOUS SERIAL BACK PLANE
App. No. 10/074,106
→
RZ RECOVERY
App. No. 10/066,982
→
HIGH SPEED CROSS POINT SWITCH ROUTING CIRCUIT WITH WORD-SYNCHRONOUS SERIAL BACK PLANE
App. No. 10/047,166
→
SCALABLE CLOCK DISTRIBUTION FOR MULTIPLE CRU ON THE SAME CHIP
App. No. 10/041,888
→
AUTOMATIC LOAD BALANCING IN SWITCH FABRICS
App. No. 10/020,491
→
LOW-DENSITY PARITY CHECK FORWARD ERROR CORRECTION
App. No. 10/044,413
→
MONOLITHIC LOSS-OF-SIGNAL DETECT CIRCUITRY
App. No. 09/976,511
→
PRECISION ON-CHIP TRANSMISSION LINE TERMINATION
App. No. 09/974,451
→
ACTUATOR-CONTROLLED MIRROR WITH Z-STOP MECHANISM
App. No. 09/956,609
→
PROGRAMMABLE ANALOG TAPPED DELAY LINE FILTER HAVING CASCADED DIFFERENTIAL DELAY CELLS
App. No. 09/955,563
→
METHOD AND APPARATUS FOR IMPROVED HIGH-SPEED ADAPTIVE EQUALIZATION
App. No. 09/955,278
→
OUTPUT DRIVER FOR HIGH SPEED ETHERNET TRANSCEIVER
App. No. 09/894,388
→
LIMITING AMPLIFIER MODULATOR DRIVER
App. No. 09/892,807
→
TRANSPARENT TRANSPORT OVERHEAD MAPPING
App. No. 09/882,582
→
CROSSPOINT SWITCH WITH SWITCH MATRIX MODULE
App. No. 09/878,054
→
PRODUCT CODE BASED FORWARD ERROR CORRECTION SYSTEM
App. No. 09/874,158
→
REDUCED GMII WITH INTERNAL TIMING COMPENSATION
App. No. 09/870,394
→
CLOCK BUFFER WITH DC OFFSET SUPPRESSION
App. No. 09/865,008
→
PAD CALIBRATION CIRCUIT WITH ON-CHIP RESISTOR
App. No. 09/850,530
→
APPARATUS AND METHOD FOR ANGLED COAXIAL TO PLANAR STRUCTURE BROADBAND TRANSITION
App. No. 09/837,615
→