IP Library Granted Patent US 8,705,603
Granted Patent B2
US 8,705,603 · App. 12/366,544 · Granted Apr 22, 2014

Adaptive data recovery system with input signal equalization

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Quick Facts
Patent No.
US 8,705,603
App. No.
12/366,544
Granted
Apr 22, 2014
Kind
B2
Abstract

Data receivers often include equalizers for operating on received signals. The equalizers often have a plurality of taps, with signals from each tap weighted based on tap settings or values. The tap settings may be set based on bit error rates of data output from the equalizer. In some embodiments data output from the equalizer is split into two signals, and the two signals are processed to indicate a data eye of the data output from the equalizer. Preferred tap settings may be determined by setting tap settings to different values and using tap settings expected to maximize the data eye. This may be performed separately for different bit settings in an attempt to reduce effects of inter-signal interference.

Claims (37)

1. A method for setting tap values for an adaptive equalizer, comprising:

setting the tap values for an adaptive equalizer to a first set of values;

for a plurality of different data cells, sampling and comparing an output of the adaptive equalizer at a first phase and first voltage, the first phase and the first voltage being within a data cell of the output of the adaptive equalizer;

for the plurality of different data cells, sampling and comparing the output of the adaptive equalizer at a second phase and second voltage, the second phase and the second voltage being within the data cell of the output of the adaptive equalizer;

determining if the sampled and compared output of the adaptive equalizer at the first phase and first voltage matches the sampled and compared output of the adaptive equalizer at the second phase and second voltage and the sampled and compared output at the first phase and voltage for at least some of the plurality of different data cells matches a predefined bit pattern; and

adjusting at least one tap value for the adaptive equalizer based on a determination that the sampled and compared output of the adaptive equalizer at the first phase and first voltage does not match the sampled and compared output of the adaptive equalizer at the second phase and second voltage.

2. The method of claim 1 further comprising performing, a plurality of times, each time of the plurality of times for different data cells:

sampling and comparing the output of the adaptive equalizer at the first phase and first voltage,

sampling and comparing the output of the adaptive equalizer at the second phase and second voltage, and

determining if the sampled and compared output of the adaptive equalizer at the first phase and first voltage matches the sampled and compared output of the adaptive equalizer at the second phase and second voltage.

3. The method of claim 2 wherein the adjusting at least one tap value for the adaptive equalizer based on the determination that the sampled and compared output of the adaptive equalizer at the first phase and first voltage does not match the sampled and compared output of the adaptive equalizer at the second phase and second voltage comprises adjusting at least one tap value for the adaptive equalizer based on a number of times the sampled and compared output of the adaptive equalizer at the first phase and first voltage does not match the sampled and compared output of the adaptive equalizer at the second phase and second voltage.

4. The method of claim 3 , wherein the sampled and compared data cell from the output of the adaptive equalizer is a data cell within the predetermined bit pattern.

5. The method of claim 4 wherein the adjusting at least one tap value is based on the number of times the sampled and compared output of the adaptive equalizer at the first phase and the first voltage does not match the sampled and compared output of the adaptive equalizer at the second phase and the second voltage for a particular data cell within the different data cells matching the predefined bit pattern.

6. The method of claim 4 further comprising changing the predefined bit pattern over time.

7. The method of claim 2 further comprising, for each of a plurality of different tap values, performing, a plurality of times, each time of the plurality of times for different data cells:

sampling and comparing the output of the adaptive equalizer at the first phase and first voltage,

sampling and comparing the output of the adaptive equalizer at the second phase and second voltage, and

determining if the sampled and compared output of the adaptive equalizer at the first phase and first voltage matches the sampled and compared output of the adaptive equalizer at the second phase and second voltage.

8. The method of claim 7 wherein the adjusting at least one tap value for the adaptive equalizer based on the determination that the sampled and compared output of the adaptive equalizer at the first phase and first voltage does not match the sampled and compared output of the adaptive equalizer at the second phase and second voltage comprises setting the tap values to the tap value of the plurality of different tap values for which the sampled and compared output of the adaptive equalizer at the first phase and first voltage does not match the sampled and compared output of the adaptive equalizer at the second phase and second voltage the least number of times.

9. The method of claim 1 wherein only one of either the first phase and the second phase or the first voltage and second voltage are different.

10. The method of claim 1 further comprising changing at least one of the first phase and the first voltage over time.

11. Circuitry for setting tap values for an equalizer, comprising:

first data recovery circuitry configured to recover data from a data stream, the data stream being recovered from an output of the equalizer;

second data recovery circuitry configured to recover data from the data stream, the data stream being recovered from the output of the equalizer;

comparison circuitry configured to compare data recovered from the first data recovery circuitry with data recovered from the second data recovery circuitry when data recovered from at least one of the first data recovery circuitry or the second data recovery circuitry matches a predefined bit pattern;

counting circuitry configured to count a number of times the comparison circuitry indicates data recovered from the first data recovery circuitry does not match data recovered from the second data recovery circuitry;

control circuitry configured to set at least one tap value of the equalizer based on the number of counted times.

12. The circuitry of claim 11 wherein the comparison circuitry is further configured to compare at least one of the data recovered from the first data recovery circuitry and the data recovered from the second data recovery circuitry with a predefined bit pattern.

13. The circuitry of claim 12 wherein the comparison circuitry is further configured to indicate that data recovered from the first data recovery circuitry does not match data recovered from the second data recovery circuitry only for data included in the predefined bit pattern.

14. The circuitry of claim 13 wherein the control circuitry is configured to set the tap values to a plurality of different sets of tap values, and to select a one set of tap values of the plurality of different sets of tap values based on the set of tap values of the plurality of different sets of tap values with the least number of counted times.

15. The circuitry of claim 14 further comprising equalizer circuitry implementing the equalizer, the equalizer circuitry including a summer for summing outputs of taps of the equalizer, the summer including an inductively peaked cascade stage.

16. A method of determining tap values for an equalizer in a receiver comprising:

setting tap values to a plurality of different sets of values and, for each of the plurality of different sets of values:

recovering data output from the equalizer in a first data channel and recovering data output from the equalizer in a second data channel; and

determining a number of times data recovered from the first data channel does not match data recovered from the second data channel and whether the output of one of the first data and the second data channel matches a predefined bit pattern; and

setting, the tap values to a one of the plurality of different sets of values for which the number of times data recovered from the first data channel does not match data recovered from the second data channel indicates the lowest bit error rate.

17. The method of claim 16 further comprising, for each of the plurality of different sets of values, setting a bit pattern to a plurality of different bit patterns, and wherein determining the number of times data recovered from the first data channel does not match data recovered from the second data channel comprising determining the number of times data recovered from the first data channel does not match data recovered from the second data channel for the set bit pattern.

Assignments (23)
RELEASE OF SECURITY INTEREST Recorded Mar 14, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 060894/0437 →
RELEASE OF SECURITY INTEREST Recorded Mar 11, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059363/0001 →
RELEASE OF SECURITY INTEREST Recorded Mar 10, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059863/0400 →
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059358/0001 →
RELEASE OF SECURITY INTEREST Recorded Feb 25, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059333/0222 →
SECURITY INTEREST Recorded Jun 4, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 057935/0474 →
SECURITY INTEREST Recorded Dec 24, 2020
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 055671/0612 →
SECURITY INTEREST Recorded Jun 5, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 053468/0705 →
RELEASE OF SECURITY INTEREST Recorded May 30, 2020
From: JPMORGAN CHASE BANK, N.A, AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 053466/0011 →
SECURITY INTEREST Recorded Apr 24, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 053311/0305 →
SECURITY INTEREST Recorded Sep 18, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 047103/0206 →
SECURITY INTEREST Recorded Jun 25, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 046426/0001 →
RELEASE OF SECURITY INTEREST Recorded May 29, 2018
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: MICROSEMI CORPORATION; MICROSEMI SEMICONDUCTOR (U.S.), INC.; MICROSEMI FREQUENCY AND TIME CORPORATION; MICROSEMI COMMUNICATIONS, INC.; MICROSEMI SOC CORP.; MICROSEMI CORP. - POWER PRODUCTS GROUP; MICROSEMI CORP. - RF INTEGRATED SOLUTIONS
Reel/Frame 046251/0391 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 22, 2017
From: MICROSEMI COMMUNICATIONS, INC.
To: MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 042523/0577 →
PATENT SECURITY AGREEMENT Recorded Feb 3, 2016
From: MICROSEMI CORPORATION; MICROSEMI SEMICONDUCTOR (U.S.) INC. (F/K/A LEGERITY, INC., ZARLINK SEMICONDUCTOR (V.N.) INC., CENTELLAX, INC., AND ZARLINK SEMICONDUCTOR (U.S.) INC.); MICROSEMI FREQUENCY AND TIME CORPORATION (F/K/A SYMMETRICON, INC.); MICROSEMI COMMUNICATIONS, INC. (F/K/A VITESSE SEMICONDUCTOR CORPORATION); MICROSEMI SOC CORP. (F/K/A ACTEL CORPORATION); MICROSEMI CORP. - POWER PRODUCTS GROUP (F/K/A ADVANCED POWER TECHNOLOGY INC.); MICROSEMI CORP. - RF INTEGRATED SOLUTIONS (F/K/A AML COMMUNICATIONS, INC.)
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037691/0697 →
RELEASE OF SECURITY INTEREST Recorded Jan 19, 2016
From: BANK OF AMERICA, N.A.
To: MICROSEMI CORPORATION; MICROSEMI CORP.-ANALOG MIXED SIGNAL GROUP, A DELAWARE CORPORATION; MICROSEMI SOC CORP., A CALIFORNIA CORPORATION; MICROSEMI SEMICONDUCTOR (U.S.) INC., A DELAWARE CORPORATION; MICROSEMI FREQUENCY AND TIME CORPORATION, A DELAWARE CORPORATION; MICROSEMI COMMUNICATIONS, INC. (F/K/A VITESSE SEMICONDUCTOR CORPORATION), A DELAWARE CORPORATION; MICROSEMI CORP.-MEMORY AND STORAGE SOLUTIONS (F/K/A WHITE ELECTRONIC DESIGNS CORPORATION), AN INDIANA CORPORATION
Reel/Frame 037558/0711 →
MERGER AND CHANGE OF NAME Recorded May 13, 2015
From: VITESSE SEMICONDUCTOR CORPORATION; LLIU100 ACQUISITION CORP.
To: MICROSEMI COMMUNICATIONS, INC.
Reel/Frame 035651/0708 →
SUPPLEMENTAL SECURITY AGREEMENT Recorded Apr 29, 2015
From: MICROSEMI COMMUNICATIONS, INC.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 035532/0925 →
RELEASE OF SECURITY INTEREST Recorded Apr 28, 2015
From: WHITEBOX VSC, LTD.
To: VITESSE SEMICONDUCTOR CORPORATION
Reel/Frame 035526/0090 →
RELEASE OF SECURITY INTEREST Recorded Nov 5, 2014
From: US BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: VITESSE SEMICONDUCTOR CORPORATION
Reel/Frame 034176/0162 →
SECURITY AGREEMENT Recorded Dec 9, 2009
From: VITESSE SEMICONDUCTOR CORPORATION
To: WHITEBOX VSC, LTD.
Reel/Frame 023627/0079 →
COLLATERAL ASSIGNMENT (INTELLECTUAL PROPERTY) Recorded Nov 5, 2009
From: VITESSE SEMICONDUCTOR CORPORATION
To: U.S. BANK NATIONAL ASSOCIATION
Reel/Frame 023471/0267 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 24, 2009
From: COE, TIM; WARWAR, GREG
To: VITESSE SEMICONDUCTOR CORPORATION
Reel/Frame 023002/0525 →