Patent Assignment
Reel/Frame 037096/0315
SECURITY INTEREST
Recorded: 2015-11-20
Received: 2015-11-20
Pages: 15
Assignee
CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
39TH FLOOR, CITIBANK TOWER, CITIBANK PLAZA, 3 GARDEN ROAD, CENTRAL, HKX, HONG KONG
Covered Applications
(39)
Semiconductor Device and Method of Forming Build-Up Interconnect Structures Over a Temporary Substrate
App. No. 14/624,136
→
Semiconductor Device and Method of Forming Repassivation Layer for Robust Low Cost Fan-Out Semiconductor Package
App. No. 14/616,942
→
Semiconductor Device and Method of Forming Compliant Stress Relief Buffer Around Large Array WLCSP
App. No. 14/564,427
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH EMBEDDED COMPONENT AND METHOD OF MANUFACTURE THEREOF
App. No. 14/556,992
→
Semiconductor Device and Method of Forming Wire Bondable Fan-Out EWLB Package
App. No. 14/548,064
→
CORELESS INTEGRATED CIRCUIT PACKAGING SYSTEM AND METHOD OF MANUFACTURE THEREOF
App. No. 14/214,765
→
Semiconductor Device and Method of Making Embedded Wafer Level Chip Scale Packages
App. No. 14/139,312
→
Semiconductor Device and Method of Forming Fine Pitch RDL Over Semiconductor Die in Fan-Out Package
App. No. 14/139,614
→
SEMICONDUCTOR DEVICE AND METHOD OF WAFER THINNING INVOLVING EDGE TRIMMING AND CMP
App. No. 14/134,907
→
Semiconductor Device and Method of Reducing Warpage Using a Silicon to Encapsulant Ratio
App. No. 14/109,313
→
INTEGRATED CIRCUIT SYSTEM WITH DEBONDING ADHESIVE AND METHOD OF MANUFACTURE THEREOF
App. No. 14/038,275
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH SIDE SOLDERABLE LEADS AND METHOD OF MANUFACTURE THEREOF
App. No. 14/037,838
→
DUAL-SIDED FILM-ASSIST MOLDING PROCESS
App. No. 14/037,320
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH POSTS AND METHOD OF MANUFACTURE THEREOF
App. No. 13/966,259
→
LEADFRAME SYSTEM WITH WARP CONTROL MECHANISM AND METHOD OF MANUFACTURE THEREOF
App. No. 13/949,432
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE UNDERFILL AND METHOD OF MANUFACTURE THEREOF
App. No. 13/844,160
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH SUBSTRATE AND METHOD OF MANUFACTURE THEREOF
App. No. 13/842,582
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH UNDERFILL AND METHOD OF MANUFACTURE THEREOF
App. No. 13/842,305
→
INTEGRATED CIRCUIT HAVING STAGGERED BOND PADS AND I/O CELLS
App. No. 13/716,479
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH TRANSFERABLE TRACE LEAD FRAME
App. No. 13/714,865
→
EXPOSED INTERCONNECT FOR A PACKAGE ON PACKAGE SYSTEM
App. No. 13/589,018
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERPOSER AND METHOD OF MANUFACTURE THEREOF
App. No. 13/489,850
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH HEATSINK CAP AND METHOD OF MANUFACTURE THEREOF
App. No. 13/489,282
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERCONNECTS
App. No. 13/407,554
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH REDISTRIBUTION LAYER AND METHOD OF MANUFACTURE THEREOF
App. No. 13/221,894
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ISLAND TERMINALS AND EMBEDDED PADDLE AND METHOD OF MANUFACTURE THEREOF
App. No. 13/187,505
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH EXPOSED VERTICAL INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF
App. No. 13/166,438
→
INTEGRATED CIRCUIT PACKAGE SYSTEM EMPLOYING WAFER LEVEL CHIP SCALE PACKAGING
App. No. 12/709,425
→
LARGE DIE PACKAGE STRUCTURES AND FABRICATION METHOD THEREFOR
App. No. 12/709,073
→
METHOD FOR MAKING SEMICONDUCTOR MULTIPACKAGE MODULE INCLUDING DIE AND INVERTED LAND GRID ARRAY PACKAGE STACKED OVER BALL GRID ARRAY PACKAGE
App. No. 12/699,787
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH FAN-IN PACKAGE AND METHOD OF MANUFACTURE THEREOF
App. No. 12/561,897
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH BUMPS AND METHOD OF MANUFACTURE THEREOF
App. No. 12/487,925
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH LOCKING TERMINAL
App. No. 12/146,192
→
SEMICONDUCTOR PACKAGE SYSTEM WITH CUT MULTIPLE LEAD PADS
App. No. 12/131,037
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH PLANAR INTERCONNECT
App. No. 12/055,526
→
STACKABLE MULTI-CHIP PACKAGE SYSTEM
App. No. 11/754,603
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH MOUNTING FEATURES FOR CLEARANCE
App. No. 11/694,913
→
METHOD OF FABRICATING A SEMICONDUCTOR ASSEMBLY INCLUDING CHIP SCALE PACKAGE AND SECOND SUBSTRATE WITH EXPOSED SUBSTRATE SURFACES ON UPPER AND LOWER SIDES
App. No. 11/626,232
→
FABRICATION METHOD FOR SEMICONDUCTOR PACKAGE HEAT SPREADERS
App. No. 10/721,916
→