Patent Assignment
Reel/Frame 038378/0219
CHANGE OF NAME
Recorded: 2016-04-07
Received: 2016-04-07
Pages: 8
Assignor
STATS CHIPPAC LTD.
Executed: 2016-03-29
Assignee
STATS CHIPPAC PTE. LTE.
5 YISHUN STREET 23, SINGAPORE, SGX, SINGAPORE
Covered Applications
(58)
SOLDER JOINT FLIP CHIP INTERCONNECTION
App. No. 13/756,905
→
PACKAGE-ON-PACKAGE SYSTEM WITH THROUGH VIAS AND METHOD OF MANUFACTURE THEREOF
App. No. 13/679,615
→
Semiconductor Device and Method for Forming Passive Circuit Elements With Through Silicon Vias to Backside Interconnect Structures
App. No. 13/615,308
→
Semiconductor Device and Method of Dual-Molding Die Formed on Opposite Sides of Build-Up Interconnect Structure
App. No. 13/559,430
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH GRID-ARRAY MECHANISM AND METHOD OF MANUFACTURE THEREOF
App. No. 13/542,120
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH TIEBAR-LESS DESIGN AND METHOD OF MANUFACTURE THEREOF
App. No. 13/523,261
→
LEADFRAME-BASED MOLD ARRAY PACKAGE HEAT SPREADER AND FABRICATION METHOD THEREFOR
App. No. 13/492,765
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PAD CONNECTION AND METHOD OF MANUFACTURE THEREOF
App. No. 13/426,442
→
OPTICAL SEMICONDUCTOR DEVICE HAVING PRE-MOLDED LEADFRAME WITH WINDOW AND METHOD THEREFOR
App. No. 13/419,242
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING NON-LINEAR INTERCONNECT LAYER WITH EXTENDED LENGTH FOR JOINT RELIABILITY
App. No. 13/417,034
→
SEMICONDUCTOR DEVICE HAVING CONDUCTIVE VIAS IN PERIPHERAL REGION CONNECTING SHIELDING LAYER TO GROUND
App. No. 13/360,549
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE-ON-PACKAGE AND METHOD OF MANUFACTURE THEREOF
App. No. 13/326,891
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CONTACTS AND METHOD OF MANUFACTURE THEREOF
App. No. 13/326,728
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING VERTICAL INTERCONNECT STRUCTURE WITH CONDUCTIVE MICRO VIA ARRAY FOR 3-D FO-WLCSP
App. No. 13/326,128
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING THICK ENCAPSULANT FOR STIFFNESS WITH RECESSES FOR STRESS RELIEF IN FO-WLCSP
App. No. 13/315,010
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING INTEGRATED PASSIVE DEVICE OVER SEMICONDUCTOR DIE WITH CONDUCTIVE BRIDGE AND FAN-OUT REDISTRIBUTION LAYER
App. No. 13/311,266
→
INTEGRATED CIRCUIT SYSTEM WITH TEST PADS AND METHOD OF MANUFACTURE THEREOF
App. No. 13/239,373
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING PROTECTION AND SUPPORT STRUCTURE FOR CONDUCTIVE INTERCONNECT STRUCTURE
App. No. 13/239,080
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH DUAL SIDE MOLD AND METHOD OF MANUFACTURE THEREOF
App. No. 13/235,202
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH LAMINATE BASE
App. No. 13/196,279
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING INTERCONNECT STRUCTURE OVER SEED LAYER ON CONTACT PAD OF SEMICONDUCTOR DIE WITHOUT UNDERCUTTING SEED LAYER BENEATH INTERCONNECT STRUCTURE
App. No. 13/167,487
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH SUPPORT STRUCTURE AND METHOD OF MANUFACTURE THEREOF
App. No. 13/164,114
→
METHOD OF MANUFACTURING INTEGRATED CIRCUIT PACKAGING SYSTEM WITH SUPPORT STRUCTURE
App. No. 13/163,643
→
INTEGRATED CIRCUIT PROTRUDING PAD PACKAGE SYSTEM AND METHOD FOR MANUFACTURING THEREOF
App. No. 13/154,308
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERLOCK AND METHOD OF MANUFACTURE THEREOF
App. No. 13/118,214
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERCONNECT AND METHOD OF MANUFACTURE THEREOF
App. No. 13/105,814
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LOCKING INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF
App. No. 13/071,433
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF
App. No. 13/053,142
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH STEP MOLD AND METHOD OF MANUFACTURE THEREOF
App. No. 13/052,590
→
Semiconductor Device and Method of Forming Conductive THV and RDL on Opposite Sides of Semiconductor Die for RDL-to-RDL Bonding
App. No. 13/034,133
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING MULTI-LAYERED UBM WITH INTERMEDIATE INSULATING BUFFER LAYER TO REDUCE STRESS FOR SEMICONDUCTOR WAFER
App. No. 13/031,546
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING PROTECTIVE STRUCTURE AROUND SEMICONDUCTOR DIE FOR LOCALIZED PLANARIZATION OF INSULATING LAYER
App. No. 12/891,232
→
Semiconductor Device and Method of Forming Through Hole Vias in Die Extension Region Around Periphery of Die
App. No. 12/858,593
→
Semiconductor Device and Method of Forming Protective Layer Over Exposed Surfaces of Semiconductor Die
App. No. 12/837,562
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH INTEGRAL INNER LEAD AND PADDLE AND METHOD OF MANUFACTURE THEREOF
App. No. 12/823,079
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LEADFRAME AND METHOD OF MANUFACTURE THEREOF
App. No. 12/818,750
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH REINFORCED ENCAPSULANT HAVING EMBEDDED INTERCONNECT AND METHOD OF MANUFACTURE THEREOF
App. No. 12/777,415
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING THROUGH VIAS WITH REFLOWED CONDUCTIVE MATERIAL
App. No. 12/775,338
→
INTEGRATED CIRCUIT PACKAGE SYSTEM AND METHOD OF MANUFACTURE THEREOF
App. No. 12/723,596
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ENCAPSULATED CONNECTOR AND METHOD OF MANUFACTURE THEREOF
App. No. 12/714,431
→
STACKED INTEGRATED CIRCUIT PACKAGE-IN-PACKAGE SYSTEM AND METHOD OF MANUFACTURE THEREOF
App. No. 12/612,603
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE-ON-PACKAGE STACKING AND METHOD OF MANUFACTURE THEREOF
App. No. 12/580,933
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH THROUGH SILICON VIA BASE AND METHOD OF MANUFACTURE THEREOF
App. No. 12/534,029
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH AN INTERPOSER AND METHOD OF MANUFACTURE THEREOF
App. No. 12/408,670
→
MOCK BUMP SYSTEM FOR FLIP CHIP INTEGRATED CIRCUITS
App. No. 12/184,219
→
MOCK BUMP SYSTEM FOR FLIP CHIP INTEGRATED CIRCUITS
App. No. 12/055,665
→
FLIP CHIP INTERCONNECTION SYSTEM HAVING SOLDER POSITION CONTROL MECHANISM
App. No. 12/051,246
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH WAFER SCALE HEAT SLUG
App. No. 12/022,296
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH FLEX BUMP
App. No. 11/773,886
→
INTEGRATED CIRCUIT PACKAGE SYSTEM EMPLOYING MULTI-PACKAGE MODULE TECHNIQUES
App. No. 11/687,357
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH BUMP OVER VIA
App. No. 11/673,558
→
DUAL-DIE PACKAGE STRUCTURE HAVING DIES EXTERNALLY AND SIMULTANEOUSLY CONNECTED VIA BUMP ELECTRODES AND BOND WIRES
App. No. 11/536,502
→
WORKPIECE DISPLACEMENT SYSTEM
App. No. 11/465,769
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ULTRA-THIN DIE
App. No. 11/456,554
→
Plasma display panel device with fluorescent layer protector
App. No. 11/397,018
→
PADLESS DIE SUPPORT INTEGRATED CIRCUIT PACKAGE SYSTEM
App. No. 11/339,176
→
SEMICONDUCTOR PACKAGE SYSTEM WITH CAVITY SUBSTRATE
App. No. 11/164,336
→
ULTRA-THIN WAFER SYSTEM AND METHOD OF MANUFACTURE THEREOF
App. No. 11/163,116
→