Patent Assignment
Reel/Frame 038378/0382
CHANGE OF NAME
Recorded: 2016-04-07
Received: 2016-04-07
Pages: 9
Assignor
STATS CHIPPAC LTD.
Executed: 2016-03-29
Assignee
STATS CHIPPAC PTE. LTE.
5 YISHUN STREET 23, SINGAPORE, SGX, SINGAPORE
Covered Applications
(90)
Semiconductor Device and Method of Forming Interposer Frame Electrically Connected to Embedded Semiconductor Die
App. No. 14/596,080
→
Semiconductor Device and Method of Forming Conductive Layer Over Substrate with Vents to Channel Bump Material and Reduce Interconnect Voids
App. No. 14/572,298
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING CONDUCTIVE VIAS THROUGH INTERCONNECT STRUCTURES AND ENCAPSULANT OF WLCSP
App. No. 14/566,870
→
Semiconductor Device and Method of Forming Patterned Repassivation Openings Between RDL and UBM to Reduce Adverse Effects of Electro-Migration
App. No. 14/563,448
→
Semiconductor Device and Method of Forming a Shielding Layer Between Stacked Semiconductor Die
App. No. 14/553,358
→
Semiconductor Device and Method of Forming Interconnect Structure for Encapsulated Die Having Pre-Applied Protective Layer
App. No. 14/523,556
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING OVERLAPPING SEMICONDUCTOR DIE WITH COPLANAR VERTICAL INTERCONNECT STRUCTURE
App. No. 14/514,190
→
Semiconductor Device and Method for Forming Openings and Trenches in Insulating Layer by First LDA and Second LDA for RDL Formation
App. No. 14/512,614
→
Semiconductor Device and Method of Forming Thermal Lid for Balancing Warpage and Thermal Management
App. No. 14/509,785
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING INTERCONNECT STRUCTURE OVER SEED LAYER ON CONTACT PAD OF SEMICONDUCTOR DIE WITHOUT UNDERCUTTING SEED LAYER BENEATH INTERCONNECT STRUCTURE
App. No. 14/503,698
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING PAD LAYOUT FOR FLIPCHIP SEMICONDUCTOR DIE
App. No. 14/503,086
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING SACRIFICIAL PROTECTIVE LAYER TO PROTECT SEMICONDUCTOR DIE EDGE DURING SINGULATION
App. No. 14/494,508
→
SEMICONDUCTOR DEVICE AND METHOD OF USING LEADFRAME BODIES TO FORM OPENINGS THROUGH ENCAPSULANT FOR VERTICAL INTERCONNECT OF SEMICONDUCTOR DIE
App. No. 14/466,923
→
Semiconductor Device and Method of Forming Interconnect Structure and Mounting Semiconductor Die in Recessed Encapsulant
App. No. 14/462,347
→
SEMICONDUCTOR DEVICE AND METHOD OF MAKING WAFER LEVEL CHIP SCALE PACKAGE
App. No. 14/449,914
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING INSULATING LAYER AROUND SEMICONDUCTOR DIE
App. No. 14/449,869
→
Integrated Circuit Package System with Removable Backing Element Having Plated Terminal Leads and Method of Manufacture Thereof
App. No. 14/340,436
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING ADHESIVE MATERIAL TO SECURE SEMICONDUCTOR DIE TO CARRIER IN WLCSP
App. No. 14/340,187
→
Semiconductor Device and Method of Forming Duplex Plated Bump-On-Lead Pad Over Substrate for Finer Pitch Between Adjacent Traces
App. No. 14/334,229
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING INDUCTOR OVER INSULATING MATERIAL FILLED TRENCH IN SUBSTRATE
App. No. 14/332,631
→
Semiconductor Device and Method of Forming Shielding Layer Over Semiconductor Die Mounted to TSV Interposer
App. No. 14/331,050
→
Semiconductor Device and Method of Forming Stacked Semiconductor Die and Conductive Interconnect Structure Through an Encapsulant
App. No. 14/330,704
→
SEMICONDUCTOR DEVICE AND METHOD OF BALANCING SURFACES OF AN EMBEDDED PCB UNIT WITH A DUMMY COPPER PATTERN
App. No. 14/329,464
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING HIGH ROUTING DENSITY INTERCONNECT SITES ON SUBSTRATE
App. No. 14/329,162
→
Semiconductor Device and Method of Forming Bump Structure with Insulating Buffer Layer to Reduce Stress on Semiconductor Wafer
App. No. 14/328,922
→
STACKABLE PACKAGE BY USING INTERNAL STACKING MODULES
App. No. 14/328,348
→
SEMICONDUCTOR METHOD AND DEVICE OF FORMING A FAN-OUT POP DEVICE WITH PWB VERTICAL INTERCONNECT UNITS
App. No. 14/326,789
→
Semiconductor Device and Method of Forming TMV and TSV in WLCSP Using Same Carrier
App. No. 14/326,237
→
Semiconductor Device and Method of Forming Bump Interconnect Structure with Conductive Layer Over Buffer Layer
App. No. 14/321,370
→
SOLDER JOINT FLIP CHIP INTERCONNECTION
App. No. 14/305,185
→
Semiconductor Device and Method of Forming Shielding Layer Over Active Surface of Semiconductor Die
App. No. 14/303,484
→
Semiconductor Device Including RDL Along Sloped Side Surface of Semiconductor Die for Z-Direction Interconnect
App. No. 14/292,925
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING UBM STRUCTURE ON BACK SURFACE OF TSV SEMICONDUCTOR WAFER
App. No. 14/288,589
→
Semiconductor Device and Method of Forming an Inductor on Polymer Matrix Composite Substrate
App. No. 14/289,344
→
Semiconductor Device and Method of Forming Repassivation Layer with Reduced Opening to Contact Pad of Semiconductor Die
App. No. 14/284,752
→
Semiconductor Device and Method of Forming a Dual UBM Structure for Lead Free Bump Connections
App. No. 14/275,213
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING INSULATING LAYER DISPOSED OVER THE SEMICONDUCTOR DIE FOR STRESS RELIEF
App. No. 14/274,599
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING MICRO-VIAS PARTIALLY THROUGH INSULATING MATERIAL AROUND BUMP INTERCONNECT
App. No. 14/268,316
→
Semiconductor Device and Method of Forming a Vertical Interconnect Structure for 3-D FO-WLCSP
App. No. 14/267,800
→
Semiconductor Device and Method of Forming Topside and Bottom-side Interconnect Structures Around Core Die with TSV
App. No. 14/267,777
→
SEMICONDUCTOR DEVICE AND METHOD OF EMBEDDING BUMPS FORMED ON SEMICONDUCTOR DIE INTO PENETRABLE ADHESIVE LAYER TO REDUCE DIE SHIFTING DURING ENCAPSULATION
App. No. 14/265,782
→
Semiconductor Device and Method of Stacking Semiconductor Die on a Fan-Out WLCSP
App. No. 14/261,252
→
Semiconductor Device and Method of Confining Conductive Bump Material During Reflow with Solder Mask Patch
App. No. 14/258,300
→
Semiconductor Device and Method of Forming Insulating Layer in Notches Around Conductive TSV for Stress Relief
App. No. 14/257,850
→
Semiconductor Device with Conductive Pillars Having Recesses or Protrusions to Detect Interconnect Continuity Between Semiconductor Die and Substrate
App. No. 14/256,047
→
Semiconductor Device and Method of Forming Conductive Vias with Trench in Saw Street
App. No. 14/249,307
→
SEMICONDUCTOR DEVICE AND METHOD OF PROVIDING Z-INTERCONNECT CONDUCTIVE PILLARS WITH INNER POLYMER CORE
App. No. 14/224,931
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING STRESS-REDUCED CONDUCTIVE JOINT STRUCTURES
App. No. 14/223,695
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING CONDUCTIVE VIAS USING BACKSIDE VIA REVEAL AND SELECTIVE PASSIVATION
App. No. 14/222,547
→
EXTENDED REDISTRIBUTION LAYERS BUMPED WAFER
App. No. 14/214,120
→
Semiconductor Device and Method of Forming Discontinuous ESD Protection Layers Between Semiconductor Die
App. No. 14/194,691
→
Semiconductor Device and Method of Forming Embedded Conductive Layer for Power/Ground Planes in FO-EWLB
App. No. 14/193,267
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING INTERCONNECT STRUCTURE WITH CONDUCTIVE PADS HAVING EXPANDED INTERCONNECT SURFACE AREA FOR ENHANCED INTERCONNECTION PROPERTIES
App. No. 14/192,706
→
Semiconductor Device and Method of Forming Ultra High Density Embedded Semiconductor Die Package
App. No. 14/187,014
→
Semiconductor Device and Method of Forming Embedded Wafer Level Chip Scale Packages
App. No. 14/070,509
→
SEMICONDUCTOR DEVICE AND METHOD OF MAKING BUMPLESS FLIPCHIP INTERCONNECT STRUCTURES
App. No. 14/039,418
→
Semiconductor Device and Method of Bonding Semiconductor Die to Substrate in Reconstituted Wafer Form
App. No. 14/039,092
→
SEMICONDUCTOR DEVICE AND METHOD OF SIMULTANEOUS MOLDING AND THERMALCOMPRESSION BONDING
App. No. 14/038,339
→
Semiconductor Device and Method of Using a Standardized Carrier to Form Embedded Wafer Level Chip Scale Packages
App. No. 14/036,525
→
Semiconductor Device and Method of Controlling Warpage in Reconstituted Wafer
App. No. 14/036,193
→
Semiconductor Device and Method of Forming Dual Fan-Out Semiconductor Package
App. No. 14/035,726
→
Bump-on-Lead Flip Chip Interconnection
App. No. 13/965,356
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING THROUGH MOLD HOLE WITH ALIGNMENT AND DIMENSION CONTROL
App. No. 13/950,122
→
Semiconductor Device and Method of Using Substrate With Conductive Posts and Protective Layers to Form Embedded Sensor Die Package
App. No. 13/930,980
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING LOW PROFILE 3D FAN-OUT PACKAGE
App. No. 13/931,397
→
Methods of Forming Conductive Materials on Contact Pads
App. No. 13/929,767
→
Semiconductor Device and Method of Forming Trench and Disposing Semiconductor Die Over Substrate to Control Outward Flow of Underfill Material
App. No. 13/929,485
→
Semiconductor Device and Method of Forming an Interposer Including a Beveled Edge
App. No. 13/929,426
→
Semiconductor Device and Method of Individual Die Bonding Followed by Simultaneous Multiple Die Thermal Compression Bonding
App. No. 13/928,862
→
Methods of Forming Conductive and Insulating Layers
App. No. 13/929,776
→
METHODS OF FORMING CONDUCTIVE JUMPER TRACES
App. No. 13/929,775
→
SEMICONDUCTOR DEVICE AND METHOD OF MAKING AN EMBEDDED WAFER LEVEL BALL GRID ARRAY (EWLB) PACKAGE ON PACKAGE (POP) DEVICE WITH A SLOTTED METAL CARRIER INTERPOSER
App. No. 13/918,103
→
Methods of Manufacturing Flip Chip Semiconductor Packages Using Double-Sided Thermal Compression Bonding
App. No. 13/853,810
→
SEMICONDUCTOR DEVICE AND METHOD OF CALIBRATING WARPAGE TESTING SYSTEM TO ACCURATELY MEASURE SEMICONDUCTOR PACKAGE WARPAGE
App. No. 13/846,593
→
SEMICONDUCTOR DEVICE AND METHOD OF USING PARTIAL WAFER SINGULATION FOR IMPROVED WAFER LEVEL EMBEDDED SYSTEM IN PACKAGE
App. No. 13/801,675
→
Semiconductor Device and Method of Forming WLCSP with Semiconductor Die Embedded within Interconnect Structure
App. No. 13/801,294
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING STRESS RELIEVING VIAS FOR IMPROVED FAN-OUT WLCSP PACKAGE
App. No. 13/759,911
→
Semiconductor Device and Method of Forming Through-Silicon-Via with Sacrificial Layer
App. No. 13/743,054
→
Flip Chip Interconnect Solder Mask
App. No. 13/596,860
→
FLIP CHIP INTERCONNECT SOLDER MASK
App. No. 13/596,446
→
Semiconductor Device and Method of Forming a Metallurgical Interconnection Between a Chip and a Substrate in a Flip Chip Package
App. No. 13/268,048
→
SEMICONDUCTOR PACKAGING STRUCTURE AND METHOD OF FORMING METALLURGICAL INTERCONNECTION DIRECTLY BETWEEN A DUP AND METALLIZATION ON A SUBTRATE
App. No. 13/245,181
→
Semiconductor Device and Method of Forming Interconnect Structure for Encapsulated Die Having Pre-Applied Protective Layer
App. No. 13/207,633
→
METHODS FOR PRODUCING PHOTOSENSITIVE MICROPARTICLES, NON-AQUEOUS DISPERSIONS THEREOF AND ARTICLES PREPARED THEREWITH
App. No. 12/719,293
→
Apparatus and process for precise encapsulation of flip chip interconnects
App. No. 12/018,441
→
INTEGRATED CIRCUIT PACKAGE-IN-PACKAGE SYSTEM
App. No. 11/276,941
→
ETCHED LEADFRAME FLIPCHIP PACKAGE SYSTEM
App. No. 11/307,384
→
Semiconductor multi-package module having inverted second package stacked over die-down flip-chip ball grid array (BGA) package
App. No. 11/337,168
→
SEMICONDUCTOR PACKAGE FOR A LARGE DIE
App. No. 11/169,850
→
SEMICONDUCTOR MULTIPACKAGE MODULE INCLUDING PROCESSOR AND MEMORY PACKAGE ASSEMBLIES
App. No. 10/618,933
→