Semiconductor device and method of forming pad layout for flipchip semiconductor die
A semiconductor device has a semiconductor die with a die pad layout. Signal pads in the die pad layout are located primarily near a perimeter of the semiconductor die, and power pads and ground pads are located primarily inboard from the signal pads. The signal pads are arranged in a peripheral row or in a peripheral array generally parallel to an edge of the semiconductor die. Bumps are formed over the signal pads, power pads, and ground pads. The bumps can have a fusible portion and non-fusible portion. Conductive traces with interconnect sites are formed over a substrate. The bumps are wider than the interconnect sites. The bumps are bonded to the interconnect sites so that the bumps cover a top surface and side surfaces of the interconnect sites. An encapsulant is deposited around the bumps between the semiconductor die and substrate.
1. A method of making a semiconductor device, comprising:
providing a semiconductor die;
providing a substrate;
forming a plurality of conductive traces including a plurality of interconnect sites over the substrate arranged in a layout comprising signal sites located primarily in a perimeter region of the substrate;
forming a plurality of physically separate solder mask patches disposed interstitially between and physically isolated from the interconnect sites; and
disposing an interconnect structure between the semiconductor die and substrate, wherein a width of the interconnect structure is greater than a width of the interconnect sites and the interconnect structure covers a side surface of the conductive traces.
2. The method of claim 1 , wherein the substrate is a four-metal layer substrate.
3. The method of claim 1 , wherein the interconnect structure includes a fusible portion and non-fusible portion.
4. The method of claim 1 , further including arranging the signal sites in a peripheral array generally parallel to an edge of the substrate.
5. The method of claim 1 , further including arranging the signal sites in adjacent rows in a staggered arrangement or orthogonal arrangement.
6. The method of claim 1 , further including depositing an encapsulant over the semiconductor die and substrate.
7. A method of making a semiconductor device, comprising:
providing a substrate;
forming a plurality of conductive traces including interconnect sites on the conductive traces and disposed over the substrate arranged in a layout comprising signal sites located primarily in a perimeter region of the substrate;
forming a plurality of physically separate solder mask patches disposed interstitially between and physically isolated from the interconnect sites; and
disposing a semiconductor die over the substrate with an interconnect structure between the semiconductor die and substrate, wherein the interconnect structure covers a side surface of the conductive traces.
8. The method of claim 7 , wherein the substrate includes no more than four metal layers.
9. The method of claim 7 , wherein the interconnect structure includes a fusible portion and non-fusible portion between the semiconductor die and substrate.
10. The method of claim 7 , wherein a width of the interconnect structure is greater than a width of a first interconnect site.
11. The method of claim 7 , wherein the interconnect sites include power sites and ground sites and fewer than 10% of the power sites and ground sites are located within the perimeter region.
12. The method of claim 7 , wherein greater than 90% of the signal sites are located within the perimeter region.
13. The method of claim 7 , further including arranging the signal sites in a peripheral row or in a peripheral array generally parallel to an edge of the substrate.
14. A semiconductor device, comprising:
a semiconductor die including a die pad layout comprising signal pads located primarily in a perimeter region of the semiconductor die;
a substrate;
a plurality of conductive traces including interconnect sites on the conductive traces formed over the substrate;
a plurality of physically separate solder mask patches disposed interstitially between and physically isolated from the interconnect sites; and
an interconnect structure disposed between the signal pads of the semiconductor die and the interconnect sites on the conductive traces of the substrate, wherein a width of the interconnect structure is greater than a width of the interconnect sites and the interconnect structure covers a side surface of the conductive traces.
15. The semiconductor device of claim 14 , wherein the signal pads are arranged in adjacent rows in a staggered arrangement or orthogonal arrangement.
16. The semiconductor device of claim 14 , wherein the signal pads are arranged in no more than two rows.
17. The semiconductor device of claim 14 , wherein the interconnect structure includes a fusible portion and non-fusible portion.
18. The semiconductor device of claim 14 , wherein the die pad layout includes power pad and ground pads and fewer than 10% of the power pads and ground pads are located within the perimeter region.
19. The semiconductor device of claim 14 , wherein the substrate is a four-metal layer substrate.
20. A semiconductor device, comprising:
a semiconductor die;
a substrate disposed over the semiconductor die;
a plurality of conductive traces including interconnect sites on the conductive traces formed over the substrate and arranged in a layout including signal sites located primarily in a perimeter region of the substrate;
a plurality of physically separate solder mask patches disposed interstitially between and physically isolated from the interconnect sites; and
an interconnect structure disposed between the semiconductor die and substrate, wherein the interconnect structure covers a side surface of the conductive traces.
21. The semiconductor device of claim 20 , wherein the substrate includes no more than four metal layers.
22. The semiconductor device of claim 20 , wherein the signal sites are arranged in adjacent rows in a staggered arrangement or orthogonal arrangement.
23. The semiconductor device of claim 20 , wherein the signal sites are arranged in no more than two rows.
24. The semiconductor device of claim 20 , wherein the interconnect structure includes a fusible portion and non-fusible portion disposed between the semiconductor die and the substrate.
25. The semiconductor device of claim 20 , wherein the conductive traces include power sites and ground sites and fewer than 10% of the power sites and ground sites are located within the perimeter region.