Patent Assignment
Reel/Frame 064869/0363
This Submission Is to Correct a Typographical Error in the Cover Sheet Previously Recorded on Reel: 038378 Frame: 0382 to Correct the Spelling of Assignee's Name from "Stats Chippac Pte. Lte." to "Stats Chippac Pte. Ltd."
Recorded: 2023-09-06
Pages: 13
Assignor
STATS CHIPPAC LTD.
Executed: 2016-03-29
Assignee
STATS CHIPPAC PTE. LTD.
5 YISHUN STREET 23, SINGAPORE, SINGAPORE
Covered Properties
(86)
Semiconductor Package for a Large Die
Semiconductor multi-package module having inverted second package stacked over die-down flip-chip ball grid array (BGA) package
Application:
11/337,168 →
Publication:
US 2006/0138649
Apparatus and process for precise encapsulation of flip chip interconnects
Application:
12/018,441 →
Publication:
US 2008/0134484
Semiconductor Device and Method of Forming Interconnect Structure for Encapsulated Die Having Pre-Applied Protective Layer
Semiconductor Packaging Structure and Method of Forming Metallurgical Interconnection Directly Between a Dup and Metallization on a Subtrate
Application:
13/245,181 →
Publication:
US 2012/0013005
Semiconductor Device and Method of Forming a Metallurgical Interconnection Between a Chip and a Substrate in a Flip Chip Package
Flip Chip Interconnect Solder Mask
Flip Chip Interconnect Solder Mask
Semiconductor Device and Method of Forming Through-Silicon-Via with Sacrificial Layer
Semiconductor Device and Method of Forming Stress Relieving Vias for Improved Fan-Out Wlcsp Package
Semiconductor Device and Method of Forming WLCSP with Semiconductor Die Embedded within Interconnect Structure
Semiconductor Device and Method of Using Partial Wafer Singulation for Improved Wafer Level Embedded System in Package
Semiconductor Device and Method of Calibrating Warpage Testing System to Accurately Measure Semiconductor Package Warpage
Methods of Manufacturing Flip Chip Semiconductor Packages Using Double-Sided Thermal Compression Bonding
Semiconductor Device and Method of Making an Embedded Wafer Level Ball Grid Array (Ewlb) Package on Package (Pop) Device with a Slotted Metal Carrier Interposer
Semiconductor Device and Method of Individual Die Bonding Followed by Simultaneous Multiple Die Thermal Compression Bonding
Semiconductor Device and Method of Forming an Interposer Including a Beveled Edge
Application:
13/929,426 →
Publication:
US 2015/0001741
Semiconductor Device and Method of Forming Trench and Disposing Semiconductor Die Over Substrate to Control Outward Flow of Underfill Material
Methods of Forming Conductive Materials on Contact Pads
Application:
13/929,767 →
Publication:
US 2015/0004750
Methods of Forming Conductive Jumper Traces
Methods of Forming Conductive and Insulating Layers
Semiconductor Device and Method of Using Substrate With Conductive Posts and Protective Layers to Form Embedded Sensor Die Package
Semiconductor Device and Method of Forming Low Profile 3D Fan-Out Package
Semiconductor Device and Method of Forming Through Mold Hole with Alignment and Dimension Control
Bump-on-Lead Flip Chip Interconnection
Semiconductor Device and Method of Forming Dual Fan-Out Semiconductor Package
Semiconductor Device and Method of Controlling Warpage in Reconstituted Wafer
Semiconductor Device and Method of Using a Standardized Carrier to Form Embedded Wafer Level Chip Scale Packages
Semiconductor Device and Method of Simultaneous Molding and Thermalcompression Bonding
Semiconductor Device and Method of Bonding Semiconductor Die to Substrate in Reconstituted Wafer Form
Semiconductor Device and Method of Making Bumpless Flipchip Interconnect Structures
Semiconductor Device and Method of Forming Embedded Wafer Level Chip Scale Packages
Semiconductor Device and Method of Forming Ultra High Density Embedded Semiconductor Die Package
Semiconductor Device and Method of Forming Interconnect Structure with Conductive Pads Having Expanded Interconnect Surface Area for Enhanced Interconnection Properties
Semiconductor Device and Method of Forming Embedded Conductive Layer for Power/Ground Planes in FO-EWLB
Semiconductor Device and Method of Forming Discontinuous ESD Protection Layers Between Semiconductor Die
Extended Redistribution Layers Bumped Wafer
Semiconductor Device and Method of Forming Conductive Vias Using Backside via Reveal and Selective Passivation
Semiconductor Device and Method of Forming Stress-Reduced Conductive Joint Structures
Semiconductor Device and Method of Providing Z-Interconnect Conductive Pillars with Inner Polymer Core
Semiconductor Device and Method of Forming Conductive Vias with Trench in Saw Street
Semiconductor Device with Conductive Pillars Having Recesses or Protrusions to Detect Interconnect Continuity Between Semiconductor Die and Substrate
Semiconductor Device and Method of Forming Insulating Layer in Notches Around Conductive TSV for Stress Relief
Semiconductor Device and Method of Confining Conductive Bump Material During Reflow with Solder Mask Patch
Semiconductor Device and Method of Stacking Semiconductor Die on a Fan-Out WLCSP
Semiconductor Device and Method of Embedding Bumps Formed on Semiconductor Die into Penetrable Adhesive Layer to Reduce Die Shifting During Encapsulation
Semiconductor Device and Method of Forming Topside and Bottom-side Interconnect Structures Around Core Die with TSV
Semiconductor Device and Method of Forming a Vertical Interconnect Structure for 3-D FO-WLCSP
Semiconductor Device and Method of Forming Micro-Vias Partially Through Insulating Material Around Bump Interconnect
Semiconductor Device and Method of Forming Insulating Layer Disposed Over the Semiconductor Die for Stress Relief
Semiconductor Device and Method of Forming a Dual UBM Structure for Lead Free Bump Connections
Semiconductor Device and Method of Forming Repassivation Layer with Reduced Opening to Contact Pad of Semiconductor Die
Semiconductor Device and Method of Forming Ubm Structure on Back Surface of Tsv Semiconductor Wafer
Semiconductor Device and Method of Forming an Inductor on Polymer Matrix Composite Substrate
Semiconductor Device Including RDL Along Sloped Side Surface of Semiconductor Die for Z-Direction Interconnect
Semiconductor Device and Method of Forming Shielding Layer Over Active Surface of Semiconductor Die
Solder Joint Flip Chip Interconnection
Semiconductor Device and Method of Forming Bump Interconnect Structure with Conductive Layer Over Buffer Layer
Application:
14/321,370 →
Publication:
US 2014/0312512
Semiconductor Device and Method of Forming TMV and TSV in WLCSP Using Same Carrier
Semiconductor Method and Device of Forming a Fan-Out Pop Device with Pwb Vertical Interconnect Units
Stackable Package by Using Internal Stacking Modules
Semiconductor Device and Method of Forming Bump Structure with Insulating Buffer Layer to Reduce Stress on Semiconductor Wafer
Semiconductor Device and Method of Forming High Routing Density Interconnect Sites on Substrate
Semiconductor Device and Method of Balancing Surfaces of an Embedded Pcb Unit with a Dummy Copper Pattern
Semiconductor Device and Method of Forming Stacked Semiconductor Die and Conductive Interconnect Structure Through an Encapsulant
Semiconductor Device and Method of Forming Shielding Layer Over Semiconductor Die Mounted to TSV Interposer
Semiconductor Device and Method of Forming Inductor Over Insulating Material Filled Trench in Substrate
Semiconductor Device and Method of Forming Duplex Plated Bump-On-Lead Pad Over Substrate for Finer Pitch Between Adjacent Traces
Semiconductor Device and Method of Forming Adhesive Material to Secure Semiconductor Die to Carrier in Wlcsp
Integrated Circuit Package System with Removable Backing Element Having Plated Terminal Leads and Method of Manufacture Thereof
Semiconductor Device and Method of Forming Insulating Layer Around Semiconductor Die
Semiconductor Device and Method of Making Wafer Level Chip Scale Package
Semiconductor Device and Method of Forming Interconnect Structure and Mounting Semiconductor Die in Recessed Encapsulant
Semiconductor Device and Method of Using Leadframe Bodies to Form Openings Through Encapsulant for Vertical Interconnect of Semiconductor Die
Semiconductor Device and Method of Forming Sacrificial Protective Layer to Protect Semiconductor Die Edge During Singulation
Semiconductor Device and Method of Forming Pad Layout for Flipchip Semiconductor Die
Semiconductor Device and Method of Forming Interconnect Structure Over Seed Layer on Contact Pad of Semiconductor Die Without Undercutting Seed Layer Beneath Interconnect Structure
Semiconductor Device and Method of Forming Thermal Lid for Balancing Warpage and Thermal Management
Semiconductor Device and Method for Forming Openings and Trenches in Insulating Layer by First LDA and Second LDA for RDL Formation
Semiconductor Device and Method of Forming Overlapping Semiconductor Die with Coplanar Vertical Interconnect Structure
Semiconductor Device and Method of Forming Interconnect Structure for Encapsulated Die Having Pre-Applied Protective Layer
Semiconductor Device and Method of Forming a Shielding Layer Between Stacked Semiconductor Die
Semiconductor Device and Method of Forming Patterned Repassivation Openings Between RDL and UBM to Reduce Adverse Effects of Electro-Migration
Semiconductor Device and Method of Forming Conductive Vias Through Interconnect Structures and Encapsulant of Wlcsp
Semiconductor Device and Method of Forming Conductive Layer Over Substrate with Vents to Channel Bump Material and Reduce Interconnect Voids
Semiconductor Device and Method of Forming Interposer Frame Electrically Connected to Embedded Semiconductor Die
Related Assignments
(15)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Jun 27, 2013
From: LEE, KOO HONG; LEE, TAE KEUN
To: STATS CHIPPAC, LTD.
Reel/Frame 030703/0080 →
Assignment of Assignor's Interest
Jun 27, 2013
From: CHOI, JOONYOUNG; KANG, YONGHEE; LEE, HUNTEAK; KANG, KEONTAEK
To: STATS CHIPPAC, LTD.
Reel/Frame 030699/0762 →
Assignment of Assignor's Interest
Jun 28, 2013
From: LAN, HOANG; ZHENLIANG, WANG
To: STATS CHIPPAC, LTD.
Reel/Frame 030709/0359 →
Assignment of Assignor's Interest
Jun 28, 2013
From: CHI, HEEJO; SHIN, HANGIL; KIM, KYUNGMOON
To: STATS CHIPPAC, LTD.
Reel/Frame 030710/0941 →
Merger and Change of Name
Aug 6, 2015
From: CHIPPAC, INC.; STATS CHIPPAC, INC.
To: STATS CHIPPAC, INC.
Reel/Frame 036286/0612 →
Security Interest
Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
Change of Name
Aug 6, 2015
From: ST ASSEMBLY TEST SERVICES LTD.
To: STATS CHIPPAC LTD.
Reel/Frame 036286/0590 →
Change of Name
Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0400 →
Change of Name
Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0382 →
Release of Security Interest
Dec 13, 2019
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 051285/0318 →
Assignment of Assignor's Interest
Dec 18, 2019
From: STATS CHIPPAC PTE. LTD.
To: JCET SEMICONDUCTOR (SHAOXING) CO., LTD.
Reel/Frame 051365/0680 →
Release of Security Interest
Jun 16, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 052963/0546 →
Release of Security Interest
Jun 16, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 052950/0497 →
Corrective Assignment to Correct the Assignee's Name Previously Recorded at Reel: 038378 Frame: 0400. Assignor(S) Hereby Confirms the Assignment.
Sep 5, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 064806/0593 →
Assignment of Assignor's Interest
Sep 3, 2025
From: STATS CHIPPAC PTE. LTD.
To: STATS CHIPPAC MANAGEMENT PTE. LTD.
Reel/Frame 072788/0917 →