Semiconductor device and method of forming an inductor on polymer matrix composite substrate
View Patent ↗A semiconductor device has a first insulating layer formed over a first surface of a polymer matrix composite substrate. A first conductive layer is formed over the first insulating layer. A second insulating layer is formed over the first insulating layer and first conductive layer. A second conductive layer is formed over the second insulating layer and first conductive layer. The second conductive layer is wound to exhibit inductive properties. A third conductive layer is formed between the first conductive layer and second conductive layer. A third insulating layer is formed over the second insulating layer and second conductive layer. A bump is formed over the second conductive layer. A fourth insulating layer can be formed over a second surface of the polymer matrix composite substrate. Alternatively, the fourth insulating layer can be formed over the first insulating layer prior to forming the first conductive layer.
1. A semiconductor device, comprising:
a polymer matrix composite substrate;
a first insulating layer completely covering a surface of the polymer matrix composite substrate;
an inductor formed over the first insulating layer; and
an interconnect structure formed over the inductor and first insulating layer and configured to electrically and mechanically connect the semiconductor device to a second substrate.
2. The semiconductor device of claim 1 , further including a capacitor formed over the polymer matrix composite substrate, the capacitor including,
a first conductive layer formed over the polymer matrix composite substrate;
a second insulating layer formed over the first conductive layer; and
a second conductive layer formed over the second insulating layer.
3. The semiconductor device of claim 2 , further including a third insulating layer formed over the second insulating layer.
4. The semiconductor device of claim 1 , further including a second insulating layer formed over the first insulating layer and inductor.
5. The semiconductor device of claim 1 , wherein the interconnect structure includes a bump.
6. The semiconductor device of claim 1 , further including a resistive layer formed over the polymer matrix composite substrate.
7. A semiconductor device, comprising:
a polymer matrix composite substrate;
a first insulating layer formed over the polymer matrix composite substrate;
an integrated passive device formed over the first insulating layer; and
an interconnect structure formed over the first insulating layer to couple the integrated passive device to a second substrate.
8. The semiconductor device of claim 7 , wherein the integrated passive device includes an inductor.
9. The semiconductor device of claim 7 , wherein the integrated passive device includes a capacitor comprising,
a first conductive layer formed over the polymer matrix composite substrate;
a second insulating layer formed over the first conductive layer; and
a second conductive layer formed over the second insulating layer.
10. The semiconductor device of claim 7 , wherein the interconnect structure includes a bump.
11. The semiconductor device of claim 7 , further including a resistive layer formed over the polymer matrix composite substrate.
12. The semiconductor device of claim 7 , further including a second insulating layer formed over the first insulating layer and integrated passive device.
13. The semiconductor device of claim 7 , wherein a coefficient of thermal expansion of the polymer matrix composite substrate matches a coefficient of thermal expansion of the integrated passive device.
14. A semiconductor device, comprising:
a polymer matrix composite substrate;
an integrated passive device formed over the polymer matrix composite substrate; and
an interconnect structure formed over the integrated passive device and configured to attach the semiconductor device to a second substrate.
15. The semiconductor device of claim 14 , wherein the integrated passive device includes an inductor.
16. The semiconductor device of claim 14 , wherein the integrated passive device includes a capacitor comprising,
a first conductive layer formed over the polymer matrix composite substrate;
an insulating layer formed over the first conductive layer; and
a second conductive layer formed over the insulating layer.
17. The semiconductor device of claim 14 , wherein the interconnect structure includes a bump.
18. The semiconductor device of claim 14 , further including a resistive layer formed over the polymer matrix composite substrate.
19. The semiconductor device of claim 14 , further including:
a first insulating layer formed over the polymer matrix composite substrate; and
a second insulating layer formed over the first insulating layer and integrated passive device.
20. The semiconductor device of claim 14 , wherein a coefficient of thermal expansion of the polymer matrix composite substrate matches a coefficient of thermal expansion of the integrated passive device.
21. A semiconductor device, comprising:
a polymer matrix composite substrate;
an integrated passive device formed over the polymer matrix composite substrate; and
an interconnect structure disposed over the integrated passive device to couple the integrated passive device to a second substrate.
22. The semiconductor device of claim 21 , wherein the interconnect structure includes a bump.
23. The semiconductor device of claim 22 , further including a printed circuit board, wherein the bump is bonded to the printed circuit board.
24. The semiconductor device of claim 21 , wherein a coefficient of thermal expansion of the polymer matrix composite substrate matches a coefficient of thermal expansion of the integrated passive device.