IP Library Assignment 036286/0612
Patent Assignment
Reel/Frame 036286/0612

Merger and Change of Name

Recorded: 2015-08-06 Pages: 7
Assignors
CHIPPAC, INC.
Executed: 2005-01-20
STATS CHIPPAC, INC.
Executed: 2005-01-20
Assignee
STATS CHIPPAC, INC.
2711 CENTERVILLE ROAD, SUITE 400, WILMINGTON, DELAWARE, 19808
Covered Properties (59)
Flip Chip-in-Leadframe Package and Process
Patent: 6,828,220 →
Application: 09/802,443 →
Publication: US 2002/0031902
A Method of Forming a Flip Chip Interconnection Structure
Patent: 6,815,252 →
Application: 09/802,664 →
Publication: US 2001/0055835
Plastic Ball Grid Array Package with Integral Heatsink
Patent: 6,614,123 →
Application: 09/919,763 →
Publication: US 2003/0025215
Self-Coplanarity Bumping Shape for Flip Chip
Patent: 6,940,178 →
Application: 10/080,384 →
Publication: US 2002/0151228
Apparatus and Process for Precise Encapsulation of Flip Chip Interconnnects
Patent: 6,780,682 →
Application: 10/081,425 →
Publication: US 2002/0123173
Plastic Semiconductor Package
Patent: 6,661,083 →
Application: 10/081,490 →
Publication: US 2002/0163015
Chip Scale Package with Flip Chip Interconnect
Patent: 6,737,295 →
Application: 10/081,491 →
Publication: US 2002/0151189
Tape Ball Grid Array Semiconductor Package Structure and Assembly Process
Patent: 6,549,413 →
Application: 10/082,914 →
Publication: US 2002/0127778
Method for Manufacturing Plastic Ball Grid Array with Integral Heatsink
Patent: 6,967,126 →
Application: 10/608,843 →
Publication: US 2004/0043539
Semiconductor Multipackage Module Including Processor and Memory Package Assemblies
Patent: 7,034,387 →
Application: 10/618,933 →
Publication: US 2004/0195667
Semiconductor Multi-Package Module Having Wire Bond Interconnect Between Stacked Packages
Patent: 7,064,426 →
Application: 10/632,549 →
Publication: US 2004/0061212
Semiconductor Multi-Package Module Including Stacked-Die Package and Having Wire Bond Interconnect Between Stacked Packages
Patent: 6,972,481 →
Application: 10/632,550 →
Publication: US 2004/0056277
Semiconductor Multi-Package Module Having Wire Bond Interconnect Between Stacked Packages and Having Electrical Shield
Patent: 6,838,761 →
Application: 10/632,551 →
Publication: US 2004/0065963
Semiconductor Multi-Package Module Having Package Stacked Over Die-Down Flip Chip Ball Grid Array Package and Having Wire Bond Interconnect Between Stacked Packages
Patent: 7,053,476 →
Application: 10/632,553 →
Publication: US 2004/0063246
Semiconductor Multi-Package Module Having Package Stacked Over Ball Grid Array Package and Having Wire Bond Interconnect Between Stacked Packages
Patent: 7,205,647 →
Application: 10/632,568 →
Publication: US 2004/0063242
Semiconductor Multi-Package Module Having Inverted Second Package Stacked Over Die-Up Flip-Chip Ball Grid Array (Bga) Package
Patent: 7,045,887 →
Application: 10/681,583 →
Publication: US 2004/0113254
Semiconductor Multi-Package Module Having Inverted Second Package and Including Additional Die or Stacked Package on Second Package
Patent: 7,049,691 →
Application: 10/681,584 →
Publication: US 2004/0113255
Semiconductor Multi-Package Module Having Inverted Bump Chip Carrier Second Package
Patent: 7,053,477 →
Application: 10/681,734 →
Publication: US 2004/0119152
Semiconductor Multi-Package Module Having Inverted Second Package Stacked Over Die-Up Flip-Chip Ball Grid Array (Bga) Package
Patent: 6,906,416 →
Application: 10/681,747 →
Publication: US 2004/0113275
Semiconductor Stacked Multi-Package Module Having Inverted Second Package and Electrically Shielded First Package
Patent: 6,933,598 →
Application: 10/681,833 →
Publication: US 2004/0124518
Flip Chip Interconnection Structure
Patent: 7,033,859 →
Application: 10/850,093 →
Publication: US 2004/0212098
Method and Apparatus for Flip Chip Attachment by Post Collapse Re-Melt and Re-Solidification of Bumps
Patent: 7,367,489 →
Application: 10/882,078 →
Publication: US 2005/0023327
Dbg System and Method with Adhesive Layer Severing
Patent: 7,074,695 →
Application: 10/959,713 →
Publication: US 2005/0196941
Wire Bond Capillary Tip
Patent: 7,407,080 →
Application: 10/971,202 →
Publication: US 2005/0218188
Semiconductor Chip Packaging Method with Individually Placed Film Adhesive Pieces
Patent: 7,306,971 →
Application: 10/976,601 →
Publication: US 2005/0208701
Bonding Tool for Mounting Semiconductor Chips
Patent: 7,650,688 →
Application: 10/977,047 →
Publication: US 2005/0221582
Flip Chip Interconnection Pad Layout
Patent: 7,034,391 →
Application: 10/983,898 →
Publication: US 2005/0098886
Bump-On-Lead Flip Chip Interconnection
Patent: 7,368,817 →
Application: 10/985,654 →
Publication: US 2005/0110164
Multiple chip package module having inverted package stacked over die
Patent: 8,970,049 →
Application: 11/014,257 →
Publication: US 2005/0133916
Die Attach by Temperature Gradient Lead Free Soft Solder Metal Sheet or Film
Patent: 7,690,551 →
Application: 11/027,002 →
Publication: US 2005/0156325
Semiconductor Multi-Package Module Having Inverted Second Package Stacked Over Die-Up Flip-Chip Ball Grid Array (Bga) Package
Patent: 7,101,731 →
Application: 11/059,274 →
Publication: US 2005/0148113
Adhesive/Spacer Island Structure for Stacking Over Wire Bonded Die
Patent: 8,552,551 →
Application: 11/134,845 →
Publication: US 2005/0269676
Method for Manufacturing Plastic Ball Grid Array Package with Integral Heatsink
Patent: 7,217,598 →
Application: 11/213,058 →
Publication: US 2006/0019429
Multichip Leadframe Package
Patent: 7,208,821 →
Application: 11/252,193 →
Publication: US 2006/0081967
Method for Reducing Semiconductor Die Warpage
Patent: 7,256,108 →
Application: 11/252,990 →
Publication: US 2006/0094208
Wire Bond Interconnection
Patent: 7,453,156 →
Application: 11/273,635 →
Publication: US 2006/0113665
Semiconductor Package Having Double Layer Leadframe
Patent: 7,671,451 →
Application: 11/274,925 →
Publication: US 2006/0192274
Chip Scale Package Having Flip Chip Interconnect on Die Paddle
Patent: 8,067,823 →
Application: 11/280,971 →
Publication: US 2006/0192294
Semiconductor Flip Chip Package Having Substantially Non-Collapsible Spacer
Patent: 7,880,313 →
Application: 11/282,293 →
Publication: US 2006/0192295
Semiconductor multi-package module having inverted second package stacked over die-down flip-chip ball grid array (BGA) package
Application: 11/337,168 →
Publication: US 2006/0138649
Method for Making Semiconductor Multi-Package Module Having Inverted Second Package and Including Additional Die or Package Stacked on Second Package
Patent: 7,288,434 →
Application: 11/337,821 →
Publication: US 2006/0141668
Method for Making a Semiconductor Multi-Package Module Having Inverted Bump Chip Carrier Second Package
Patent: 7,247,519 →
Application: 11/337,944 →
Publication: US 2006/0158295
Method for Making a Semiconductor Multipackage Module Including a Processor and Memory Package Assemblies
Patent: 7,306,973 →
Application: 11/355,920 →
Publication: US 2006/0151867
Method of Fabricating a Semiconductor Multi-Package Module Having Inverted Second Package Stacked Over Die-Up Flip-Chip Ball Grid Array (Bga)
Patent: 7,163,842 →
Application: 11/374,383 →
Publication: US 2006/0172459
Method for Making a Semiconductor Multi-Package Module Having Wire Bond Interconnect Between Stacked Packages
Patent: 7,279,361 →
Application: 11/374,468 →
Publication: US 2006/0172463
Semiconductor Multi-Package Module Having Package Stacked Over Die-Down Flip Chip Ball Grid Array Package and Having Wire Bond Interconnect Between Stacked Packages
Patent: 7,682,873 →
Application: 11/374,472 →
Publication: US 2006/0170091
Adhesive/Spacer Island Structure for Multiple Die Package
Patent: 8,623,704 →
Application: 11/530,841 →
Publication: US 2007/0015314
Stacked Semiconductor Package Having Adhesive/Spacer Structure and Insulation
Patent: 8,030,134 →
Application: 11/536,424 →
Publication: US 2007/0018296
Method of Fabricating a Semiconductor Multi-Package Module Having a Second Package Substrate with an Exposed Metal Layer Wire Bonded to a First Package Substrate
Patent: 7,351,610 →
Application: 11/622,993 →
Publication: US 2007/0111388
Semiconductor Multi-Package Module Having Package Stacked Over Ball Grid Array Package and Having Wire Bond Interconnect Between Stacked Packages
Patent: 7,638,363 →
Application: 11/684,265 →
Publication: US 2007/0155053
Multichip Leadframe Package
Patent: 7,436,048 →
Application: 11/686,010 →
Publication: US 2007/0152308
Plastic Ball Grid Array Package with Integral Heatsink
Patent: 8,030,756 →
Application: 11/697,433 →
Publication: US 2007/0176289
Semiconductor Multi-Package Module Having Package Stacked Over Die-Up Flip Chip Ball Grid Array Package and Having Wire Bond Interconnect Between Stacked Packages
Patent: 7,732,254 →
Application: 11/744,182 →
Publication: US 2008/0036096
Method of Fabricating a Semiconductor Multi-Package Module Having Wire Bond Interconnect Between Stacked Packages
Patent: 8,143,100 →
Application: 11/849,112 →
Publication: US 2007/0292990
Method for Making a Semiconductor Multi-Package Module Having Inverted Wire Bond Carrier Second Package
Patent: 7,494,847 →
Application: 11/880,893 →
Publication: US 2008/0020512
Method of Fabricating a Semiconductor Multipackage Module Including a Processor and Memory Package Assemblies
Patent: 7,749,807 →
Application: 11/953,857 →
Publication: US 2009/0027863
Wire Bond Interconnection
Patent: 7,745,322 →
Application: 12/032,159 →
Publication: US 2008/0135997
Semiconductor Multi-Package Module Having Package Stacked Over Die-Up Flip Chip Ball Grid Array Package and Having Wire Bond Interconnect Between Stacked Packages
Patent: 7,935,572 →
Application: 12/767,693 →
Publication: US 2010/0200966
Wire Bond Interconnection
Patent: 7,986,047 →
Application: 12/783,039 →
Publication: US 2010/0225008
Related Assignments (8)
Other recorded transfers of the patents in this record — the chain of ownership.
Security Interest Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
Change of Name Apr 7, 2016
From: STATS CHIPPAC LTD
To: STATS CHIPPAC PTE. LTE
Reel/Frame 038378/0200 →
Change of Name Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0400 →
Change of Name Apr 11, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038401/0532 →
Release of Security Interest Jun 4, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 052844/0491 →
Release of Security Interest Jun 16, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 052950/0497 →
Corrective Assignment to Correct the Correct the Spelling of Assignee's Name from "Stats Chippac Pte. Lte," to "Stats Chippac Pte. Ltd." Previously Recorded at Reel: 038401 Frame: 0532. Assignor(S) Hereby Confirms the Assignment. Sep 1, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 064803/0109 →
Corrective Assignment to Correct the Assignee's Name Previously Recorded at Reel: 038378 Frame: 0400. Assignor(S) Hereby Confirms the Assignment. Sep 5, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 064806/0593 →